Answers Database
M1.5i/2.1i; CPLD: TIG (Ignore Timing) timing constraint not supported
Record #2339
Product Family: Software
Product Line: FPGA Implementation
Product Part: Timing Analyzer
Product Version: 1.5
Problem Title:
M1.5i/2.1i; CPLD: TIG (Ignore Timing) timing constraint not supported
Problem Description:
Urgency: Standard
General Description:
The CPLD fitter software does not support the TIG constraint.
If you have a UCF file which includes the TIG constraint, the
following warning will be generated by the Optimizer:
WARNING:hi607 - Ignoring MAXDELAY:FROM:POINTA:TO:POINTB:TIG.
CPLD designs do not support point-based specifications such as
TPSYNC, TPTHRU, TIG and IGNORE.
Solution 1:
To set a timespec which ignores a particular path, you must
create separate timespec for the paths which you actually do
want to constrain.
For example, if you had used the TIG constraint to ignore one
particular path:
TIMESPEC TS01=FROM:FFS:TO:FFS:100;
TIMESPEC TS02=FROM:POINTA:TO:POINTB:TIG;
where you wanted a 100ns delay on all flip-flop paths in the
design EXCEPT from POINTA to POINTB.
This must be modified such that all the flip-flops EXCEPT
POINTA and POINTB have another TNM associated with them, for
instance, REAL_PATH, and you now timespec only REAL_PATH:
<INPUT>
TIMESPEC TS01=FROM:REAL_PATH:TO:REAL_PATH:100;
</INPUT>
End of Record #2339 - Last Modified: 07/13/99 16:10 |
