Answers Database
A schematic may be written despite error from reserved names used in design
Record #2371
Product Family: Software
Product Line: Cadence
Product Part: verilog
Problem Title:
A schematic may be written despite error from reserved names used in design
Problem Description:
Keyword: verilog, reserved
Urgency: Standard
General Description:
If the user uses reserved names such as "input" or "output" for
signals in a design, Cadence will report the error but still
allow the netlist to be written. This netlist is likely to
cause problems for other design tools.
Solution 1:
Remove/change all signals causing error messages regardless of
whether the netlist is written.
End of Record #2371 - Last Modified: 06/09/97 11:36 |
