Answers Database
M1.5i/2.1i: TRCE/Timing Analyzer: 0 paths analyzed for a TIMESPEC which should have paths
Record #2435
Product Family: Software
Product Line: FPGA Implementation
Product Part: Timing Analyzer
Product Version: 1.4
Problem Title:
M1.5i/2.1i: TRCE/Timing Analyzer: 0 paths analyzed for a TIMESPEC which should have paths
Problem Description:
Urgency: Standard
General Description:
The Timing Analyzer reports that it analyzed 0 paths for
a TIMESPEC which should apply to valid paths in the design.
Solution 1:
Generally there are three situations which cause this:
1- There are multiple timing constraints in the design which
overlap, some constraints will take precedence over others.
2- All of the paths covered by one constraint are also
covered by other, higher-priority constraints, the original
constraint is completely overridden. When this happens, the
Timing Analyzer reports 0 paths analyzed for that constraint.
3- The source or destinations are invalid.
End of Record #2435 - Last Modified: 07/13/99 16:00 |
