Xilinx Answer #2449 : Basic UCF Syntax Examples for Design Placement and Timing Constraints

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Basic UCF Syntax Examples for Design Placement and Timing Constraints

Record #2449
Problem Title:
Basic UCF Syntax Examples for Design Placement and Timing Constraints

Problem Description:
Urgency: standard

General Description:

The following is a short summation of some of the more common
.UCF constraint file directives. For a complete discussion,
refer to the DynaText manual "Libraries Guide", Chapter 13.
Also refer to the Appendix H of the QuickStart Guide to find
"M1 Constraints Guide" (which is also located at
(Xilinx File ftp://ftp.xilinx.com/pub/documentation/M1/qstart.pdf) )

Solution 1:

##########################################################
# Specifying miscellaneous constraints for logic or I/O. #
##########################################################

#------------------------
# Fast or Slow Attributes
#------------------------

# Assign an OBUF to be FAST or SLOW:

INST obuf_name FAST ; #Alternate: NET pad_net FAST;
INST obuf_name SLOW ; #Alternate: NET pad_net SLOW;

#---------------------
# MEDDELAY and NODELAY
#---------------------

# Declare an IOB input FF delay (default = MAXDELAY).
# NOTE: MEDDELAY/NODELAY can be attached to a CLB FF that is pushed
# into an IOB by the "map -pr i" option.

INST input_ff_name MEDDELAY ;
INST input_latch_name NODELAY ;

#-----
# KEEP
#-----

# To keep a net from being absorbed into a logic block

NET net_name KEEP ;

#----------------------
#Net Flag (S attribute)
#----------------------

# Saves unconnected logic from being optimized out of design
# (FPGAs only)

NET net_name S;

#-----
# INIT
#-----

# Initialize ROMs, RAMs, and registers

INST ROM_name INIT = 5555;
INST FF_name = S;

Solution 2:

#######################################################
# Basic UCF Syntax Examples For Timing Specifications #
#######################################################

# ----------------
# PERIOD TIME-SPEC
# ----------------

# The PERIOD spec. covers all timing paths that start or end at a
# register, latch, or synchronous RAM which are clocked by the reference
# net (excluding pad destinations). Also covered is the setup
# requirement of the synchronous element relative to other elements
# (ex. flip flops, pads, etc...).
# NOTE: The default unit for time is nanoseconds.

NET clk20MHz PERIOD = 50 ;
NET clk50mhz TNM = registers_50mhz ;
TIMESPEC TS01 = PERIOD : registers_50mhz : 20 ;

# ------------------
# FROM:TO TIME-SPECs
# ------------------

# FROM:TO style timespecs can be used to constrain paths between time
# groups. NOTE: Keywords: RAMS, FFS, PADS, and LATCHES are predefined
# time groups used to specify all elements of each type in a design.

TIMESPEC TS02 = FROM : PADS : TO : FFS : 36 ; TIMESPEC TS03 = FROM : FFS : TO : PADS : 36 ns ; TIMESPEC TS04 = FROM : PADS : TO : PADS : 66 ; TIMESPEC TS05 = FROM : PADS : TO : RAMS : 36 ; TIMESPEC TS06 = FROM : RAMS : TO : PADS : 35.5 ;

# NOTE: The predefined time groups, LATCHES and RAMS are not
# applicable for CPLD designs.

# ----------------
# OFFSET TIME-SPEC
# ----------------

# To automatically include clock buffer/routing delay in your "PADS:TO:
# <synchronous element> or <synchronous element>:TO:PADS timing
# specifications, use OFFSET constraints instead of FROM:TO constraints.

# For an input where the maximum clock-to-out (Tco) of the driving
# device is 10 ns:

NET in_net_name OFFSET = IN : 10 : AFTER : clk_net_name ;

# For an output where the minimum setup time (Tsu) of the device being
# driven is 5 ns:

NET out_net_name OFFSET = OUT : 5 : BEFORE : clk_net_name ;

# -------------
# TIMING IGNORE
# -------------

# If you can ignore timing of paths, use Timing Ignore (TIG). NOTE: The
# "*" character is a wild-card which can be used for bus names. A "?"
# character can be used to wild-card one character.

# Ignore timing of net reset_n:

NET : reset_n : TIG ;

# Ignore data_reg(7:0) net in instance mux_mem:

NET : mux_mem/data_reg* : TIG ;

# Ignore data_reg(7:0) net in instance mux_mem as related to a TIMESPEC
# named TS01 only:

NET : mux_mem/data_reg* : TIG = TS01 ;

# Ignore data1_sig and data2_sig nets:

NET : data?_sig : TIG ;

# ---------------
# PATH EXCEPTIONS
# ---------------

# If your design has outputs that can be slower than others, you can
# create specific timespecs similar to this example for output nets
# named out_data(7:0) and irq_n:

TIMEGRP slow_outs = PADS(out_data* : irq_n) ;
TIMEGRP fast_outs = PADS : EXCEPT : slow_outs ;
TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22 ;
TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75 ;

# If you have multi-cycle FF to FF paths, you can create a time group
# using either the TIMEGRP or TNM statements.

# WARNING: Many VHDL/verilog synthesizers do not predictably name flip
# flop Q output nets. Most synthesizers do assign predictable instance
# names to flip flops, however.

# TIMEGRP example:

TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* :
inst_path/ff_q_output_net2*);

# TNM attached to instance example:

INST inst_path/ff_instance_name1_reg* TNM = slowffs ;
INST inst_path/ff_instance_name2_reg* TNM = slowffs ;

# If a FF clock-enable is used on all flip flops of a multi-cycle path,
# you can attach TNM to the clock enable net. NOTE: TNM attached to a
# net "forward traces" to any FF, LATCH, RAM, or PAD attached to the
# net.

NET ff_clock_enable_net TNM = slowffs ;

# Example of using "slowffs" timegroup, in a FROM:TO timespec, with
# either of the three timegroup methods shown above:

TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100 ;

# ----------------
# Controlling Skew
# ----------------

# Constrain the skew or delay associate with a net.
NET any_net_name MAXSKEW = 7 ;
NET any_net_name MAXDELAY = 20 ns;

#-----------
# Priorities
#-----------

# Also, constraint priority in your .ucf file is as follows: # # highest 1. Timing Ignore (TIG) # 2. FROM : THRU : TO specs # 3. FROM : TO specs # lowest 4. PERIOD specs
#
# See the on-line documentation (dtext -> Library Reference Guide) for
# additional timespec features or additional information.

Solution 3:

######################################################
# Specifying placement constraints for logic or I/O. #
######################################################

#-----------------------------------
# Assign or Prohibit I/O pin numbers
#-----------------------------------

# Assigning I/O Pin Numbers

   ##PLCC/PQFP type packages:
   NET io_net_name LOC = P111 ;
   NET HIERARCHY_BLOCK/io_net_name LOC = P44 ;

   ##PGA/BGA type packages:
   NET io_net_name LOC = A11 ;
   NET HIERARCHY_BLOCK/io_net_name LOC = C12 ;

   ##NOTE The 'P' is only used with PLCC/PQFP type packages.

# Assigning an I/O pin to a selction of pin locations
# This example assign io_net_name to either P4, P5 or P6

NET io_net_name LOC = P4, P5, P6 ;

# Prohibit I/O pin C26 or CLBR5C3 from being used:

CONFIG PROHIBIT = C26 ;
CONFIG PROHIBIT = CLB_R5C3 ;

# Note: The Mode pins (MD0, MD1, MD2) and the Boundary Scan pins
# (TCK, TDI, TDO, TMS) can not be prohibited or assigned or an error
# may occur if these sites are prohibited from the UCF file.
# These sites are reserved sites and will only be used if
# specifically specified in the design.

#-----------------------------------
# Assigning Specific Logic Locations
#-----------------------------------

# Place a basic element (BEL) in a specific CLB. BEL = FF, LUT, RAM, etc...

INST io_buf_name LOC = P110 ;
INST instance_path/BEL_name LOC = CLB_R17C36 ;

#---------------------------
# Assigning Area Constraints
#---------------------------

# XC3000 - Place CLB logic anywhere in the top left corner of the LCA
# bounded by row F and column F.

INST logic_name LOC=AA:FF ;

# XC4000 - Place logic in the top left corner of the LCA in a 5 x 5
# area bounded by row 5 and column 5.

INST logic_name LOC=CLB_R1C1:CLB_R5C5 ;

# XC4000, XC5200 - Place BUFT anywhere in the area bounded by row 1,
# column 1 and row 2, column 8.

INST logic_name LOC=TBUF_R1C1:TBUF_R2C8 ;

# XC5200 - Place logic in any slice in the top left corner of the LCA
# bounded by row 4, column 4.

INST logic_name LOC=CLB_R1C1.LC3:CLB_R4C4..LC0 ;

# Multiple LOC Constraint Examples

# XC4000 - Place decoder on the top or bottom edge.

INST logic_name LOC=T,B ;

# XC4000 - Place CLB logic in the top left corner of the LCA in
# a 5 x 5 area, but not in the CLB in row 5, column 5.

INST logic_name LOC=CLB_R1C1:CLB_R5C5 ;
INST logic_name PROHIBIT=CLB_R5C5 ;

# XC4000 - Place logic in any CLB in column 8.

INST logic_name LOC=CLB_R*C8;

End of Record #2449 - Last Modified: 05/28/99 09:03

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