Answers Database
UNISIMS: Adding the INIT attribute to VHDL/Verilog based RAM models for RTL simulation?
Record #2684
Product Family: Software
Product Line: FPGA Implementation
Product Part: Unisim
Product Version: n/a
Problem Title:
UNISIMS: Adding the INIT attribute to VHDL/Verilog based RAM models for RTL simulation?
Problem Description:
Urgency: standard
General Description:
For HDL simulation, how is the INIT attribute passed to the UNISIM
based RAM models?
LogiBLOX ROM/RAM simulation models are created with the
initialization specified in the mem file at the time of the memory
creation and no special considerations are necessary.
For timing simulation, ROM/RAM initialization is automatically
specified in the simulation netlist and no special considerations
are necessary.
For UNISIM RTL simulation, ROM/RAM primitive initialization
other than the default value of all zeros can be performed with
either a synthesis option or can be specified within a UCF file.
Unfortunatly, these parameters are not carried through for
functional simulation before the design is implemented in the
Xilinx Alliance tools.
Solution 1:
For UNISIM RTL Verilog simulation, the user will need to provide the
INIT attribute as a defparam through the testfixture.
// Only for Simulation -- the INIT attribute will not synthesize
// Please read your synthesis vendor's documentation for passing
// the INIT attribute
// Use the defparam statement for RTL simulation.
// There is no defparam needed for Post P&R simulation.
defparam UUT.RAM0.INIT="0101", UUT.RAM1.INIT="AAAA",
UUT.RAM2.INIT="FFFF", UUT.RAM3.INIT="9428";
For post place-and-route Verilog simulation, NGD2VER will write out
post-PAR netlist with defparam statements to pass the INIT attribute.
The defparam statement is used to change parameter statements at
module instantiations.
defparam \U1/MO0_0/FGBLOCK/LUTRAM/FRAM .INIT = 16'h0102;
X_RAM16 \U1/MO0_0/FGBLOCK/LUTRAM/FRAM (
.ADR0 (addr_bus_c[0]),
.ADR1 (addr_bus_c[1]),
.ADR2 (addr_bus_c[2]),
.ADR3 (\U1/MO0_0/FGBLOCK/$1N18 ),
.IN (DATA_BUS_in[0]),
.WE (\U1/MO0_0/FGBLOCK/LUTRAM/D1_NOT_WE ),
.OUT (\U1/MO0_0/F ));
Notice that the defparam statement states that the instance
"\U1/MO0_0/FGBLOCK/LUTRAM/FRAM" change INIT value to
"16'h0102"
In conjuction with the defparam, there exists a parameter statement
within the Verilog Simprim X_RAM16 module.
module X_RAM16 (OUT, IN, WE, ADR0, ADR1, ADR2, ADR3);
parameter [15:0] INIT = 'h0000;
So, instead of the default 'h0000 value for INIT, the defparam changes
the INIT value to 16'h0102
Solution 2:
For RTL VHDL simulation, the type of Generic INIT changed for consistency with
the LUT, block RAM and shift-register LUT simulation models added to the VHDL
UNISIM and SIMPRIM libraries for Virtex support, the type of the generic INIT in
all UNISIM and SIMPRIM select RAM and ROM simulation models has been
changed from string to bit_vector. In conformance with this change, slightly
modified generic map syntax is required:
Before: INIT => "F731" (Alliance 1.4 and earlier)
Now: INIT => X"F731" (Alliance 1.5 and later)
-- Use this configuration for RTL simulation in the testbench.
-- There is no configuration needed for Post place-and-route simulation.
CONFIGURATION RTL_simulation OF testbench IS
FOR tutorial
FOR uut:rams_example
FOR xilinx
FOR RAM0 : RAM16X1S USE ENTITY UNISIM.RAM16X1S(RAM16X1S_V)
generic map (INIT => X"0101");
END FOR;
FOR RAM1 : RAM16X1S USE ENTITY UNISIM.RAM16X1S(RAM16X1S_V)
generic map (INIT => X"AAAA");
END FOR;
FOR RAM2 : RAM16X1S USE ENTITY UNISIM.RAM16X1S(RAM16X1S_V)
generic map (INIT => X"FFFF");
END FOR;
FOR RAM3 : RAM16X1S USE ENTITY UNISIM.RAM16X1S(RAM16X1S_V)
generic map (INIT => X"9428");
END FOR;
END FOR;
END FOR;
END FOR;
End of Record #2684 - Last Modified: 11/18/99 11:12 |
