Answers Database
CPLD: 9500/XL : How to control Logic Optimization in a CPLD
Record #2729
Product Family: Software
Product Line: CPLD Implementation
Product Part: hitop
Product Version: 1.3
Problem Title:
CPLD: 9500/XL : How to control Logic Optimization in a CPLD
Problem Description:
Urgency: standard
General Description:
The CPLD fitter software will collapse all the combinatorial
logic in your design, either partially or completely. You can,
however control the way the logic optimization is performed.
Solution 1:
Collapsing Product Term Limit:
When a larger combinational logic function consisting of
several levels of AND-OR logic is completely collapsed
(flattened), the number of product terms required to implement
the function may grow considerably. By default, the fitter
limits the number of p-terms used as a result of collapsing to
25 for XC9500 devices. If the collapsing of a logic level
results in a logic function consisting of more than the p-term
limit (after Boolean reduction), then the collapsing of that
logic level is not performed and the function will be
implemented using additional levels of AND-OR logic.
You can change the Pterm Collapsing Limit to any value from
2 to 90.
The fitter report (design_name.rpt) indicates the number of
p-terms used for each logic function. You should see these
numbers increase as you raise the pterms limit, until the
design is fully flattened. At the same time, you'll see the
internal combinational nodes eliminated until none remain.
Solution 2:
Preventing Collapsing of a Logic Node:
Flattening typically increases the overall amount of p-term
resources required to implement the design. Some designs which
fit the target device initially may fail to fit if flattened
too much. Other designs can be flattened completely and still
fit. If you cannot increase the pterms parameter enough to
sufficiently flatten a critical path and still fit the target
device, you may try applying the logic optimization control
attribute KEEP to specific nodes in your design so that those
nodes won't get collapsed into their fan-outs.
If you have a symbol FRED in your schematic that you do not
want to get optimized out, place the KEEP attribute on FRED.
You can also do this through a UCF file. The correct syntax is:
INST FRED KEEP;
The KEEP attribute has no effect on any symbol that contains no
macrocell logic, such as an I/O buffer.
When the KEEP attribute is placed on a symbol, it inhibits
logic optimization on all macrocells used to implement the
symbol. For example, if you place KEEP on a macro symbol (E.g.
Library Element - D2_4E), all outputs and internal nodes of the
decoder will be prevented from collapsing. This is usually not
desirable.
If you want to prevent collapsing on a specific output signal
from a macro symbol, you can place the KEEP attribute on the
net itself. When you place the KEEP attribute on a net, the
fitter applies the attribute only to the primitive symbol that
drives that net.
If you have a net JACK connected to your symbol FRED in your
schematic that you do not want to get optimized out, place the
KEEP attribute on JACK.
You can also do this through a UCF file. The correct syntax is:
NET JACK KEEP;
Solution 3:
Forcing Collapsing of a Logic Node:
You can also force a logic symbol to collapse into all of its
fanouts by placing the COLLAPSE attribute on the symbol or its output net.
The correct syntax to do this via a UCF file is :
NET NODE COLLAPSE; - on the output NET.
The COLLAPSE attribute affects all logic functions contained
within a symbol. If you want to force collapsing of a
multi-symbol logic chain, you may need to use multiple collapse
attributes.
End of Record #2729 - Last Modified: 12/30/99 10:34 |
