Answers Database
TRCE: How to analyze (the longest) nets/paths in timing constraints
Record #2740
Product Family: Software
Product Line: FPGA Implementation
Product Part: trce
Problem Title:
TRCE: How to analyze (the longest) nets/paths in timing constraints
Problem Description:
Urgency: Standard
General Description:
You can enter timing constraints to tell the place and route
software the maximum period you want on some pieces of logic
and the minimum delay that you want on other pieces of logic.
How can you analyze the path delays for a timing constraint?
The bottom of the solution describes how to find the longest
path for a timing constraint.
Solution 1:
Timing Reports:
Report Browser:
The Report Browser contains 2 timing reports:
- Logic Level Timing Report
- Post Layout Timing Report
The Logic Level Timing Report is produced after the Map stage. The
times reported are based on the actual block delays and estimates
for the route delays.
The Post Layout Timing Report is produced after the Place and
Route stage. The times reported here are based on real block and
real route delays.
To enable either report to give an analysis of the paths within
timing constraints:
1. In the Design Manager, select the revision that you are
analyzing.
2. Click on the Flow Engine button and from the Flow Engine
menu, select Setup->Options.
3. In the Options dialog, click on the Edit Template button
for the Implementation Template.
4. On the Implementation Template, click on the Timing Tab.
Make sure that **Report Paths in User Timing Constraint**
is selected.
NOTE: The Logic Level Timing Report and Post Layout Timing Report
are not produced by default. In order to produce the reports:
1. In the Design Manager, select the revision that you are
analyzing.
2. Click on the Flow Engine button and from the Flow Engine
menu, select Setup->Options.
3. In the Options dialog, select Produce Logic Level Timing
Report to enable the Flow Engine to create the Logic Level
Timing Report. Select Produce Post Layout Timing Report
to enable the Flow Engine to create the Post Layout Timing
Report. Click on OK to save the settings.
4. The Flow Engine will produce the Logic Level Timing
Report in the Map stage if the Produce Logic Level Timing
Report option is set. The Flow Engine will produce the
Post Layout Timing Report in the Timing stage if the
Produce Post Layout Timing Report option is set.
Command Line:
A post Map path analysis of timing constraints report can be
generated by running the following command:
trce <design name>.ncd <design name>.pcf -v -o <design name>.twr
- where <design name>.ncd and <design name>.pcf are
the output of map
- The timing constraint report will be in <design name>.twr
A post place and route timing constraint report can be generated
by running the following command:
trce <design name>.ncd <design name>.pcf -v -o <design name>.twr
- where <design name>.ncd and <design name>.pcf are
the output of par
- The timing constraint report will be in <design name>.twr
Sample of a Path Analysis Timing Constraint Report:
======================================================================
Timing constraint: NET "I0/CLK" PERIOD = 25 nS HIGH 50.000 % ;
1789 items analyzed, 0 timing errors detected.
Minimum period is 20.692ns.
----------------------------------------------------------------------
Slack: 4.308ns path I0/LCAD07 to I0/RR15//QX relative to
25.000ns delay constraint
Path I0/LCAD07 to I0/RR15//QX contains 4 levels of logic:
Path starting from Comp: P141.PAD
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
P141.I1 Tpid 1.180R I0/LCAD07
I0/LCAD07
I0/LCA07
CLB_R12C14.F2 net 8.776R I0/LCA07
CLB_R12C14.Y Tiho 2.140R I2/N$2726//G
I2/N$2726//G
I2/N$1978//F
TBUF_R7C10.2.T net 5.650R I2/N$1978//F
TBUF_R7C10.2.O Ton 0.800R I2/TBUF_EJ_2
CLB_R7C9.G2 net 1.237R I2/DATIN1<5>
Tick 0.909R I0/RR15//QX
I0/RR15//G
I0/RR15//QY
-------------------------------------------------
Total (24.3% logic, 75.7% route) 20.692ns (to I0/CLK)
For each timing constraint, the report will list all of the paths,
starting from worst case path to best case path. As shown above,
every path will have its subpaths enumerated. The sample above
only shows enumeration for the worstcase path in timing constraint:
NET "I0/CLK" PERIOD = 25 nS
This path starts as input at Pad 141. It travels to the F function
generator of CLB R12C14. It then enters the tri-state input
of a tri-state buffer next to CLB R7C10. It then enters the G
function generator of CLB R7C9 (a neighbor of R7C10) and includes
the setup times for both flip flops (QX and QY) in R7C9.
To find delays on a specific net, in the text editor, search for
the net name.
NOTE: The R on the delays refers to Rising.
End of Record #2740 - Last Modified: 05/28/99 09:03 | 
