Answers Database
How to analyze the delays for a specific path using M1 software?
Record #2742
Problem Title:
How to analyze the delays for a specific path using M1 software?
Problem Description:
Urgency: Standard
General Description:
How can I analyze any of the path delays between two pieces of
logic in my design?
Solution 1:
This capability is only available through the Timing Anaylyzer
graphical software.
1. In the Design Manager, select the revision that you are
analyzing.
2. Click on the Timing Analyzer button in the Design Manager
toolbox.
3. If you are already in the Timing Analyzer and have setup
some filters, select Path Filters -> Reset All Path Filters
from the menu.
4. To choose the starting points for your paths, select
Path Filters->Path Analysis Filters->Select Sources... from
the menu.
5. In the Select Sources dialog choose the Selected Sources
button. Choose the Source Element Type: Flip-Flops, Pads, Nets,
Pins, CLBs, Clocks. Use the filter to limit the choices (wild
card characters are valid). Move selected sources to the
Selected Sources group box.
6. To choose the ending points for your paths, select
Path Filters->Path Analysis Filters->Select Destinations... from
the menu.
7. In the Select Destinations dialog choose the Selected Destionations
button. Choose the Destination Element Type: Flip-Flops, Pads, Nets,
Pins, CLBs, Clocks. Use the filter to limit the choices (wild
card characters are valid). Move selected destinations to the
Selected Destinations group box.
8. To produce a timing report, select Analyze->Analyze All Paths from
menu.
9. The timing report will list all of the paths from worst case (top)
to best case (bottom).
10. If you only a few paths are reported, select Options->Report Options...
from the menu. In the Report Options dialog, select a larger number
for Maximum Paths per Timing Constraint. Then regenerate the report
as in step 8.
Sample Report Below:
================================================================================
Timing constraint: PATH "PATHFILTERS" = FROM TIMEGRP "SOURCES" TO TIMEGRP
"DESTINATIONS" ;
9909 items analyzed, 0 timing errors detected.
Maximum delay is 71.159ns.
--------------------------------------------------------------------------------
Delay: 71.159ns I0/NPD08 to I2/DAT<4>
Path I0/NPD08 to I2/DAT<4> contains 6 levels of logic:
Path starting from Comp: P85.PAD
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
P85.I1 Tpid 1.180R I0/NPD08
I0/NPD08
I0/NPDB08
CLB_R12C9.F2 net 7.971R I0/NPDB08
CLB_R12C9.X Tilo 1.300R I2/N$2726//F
I2/N$2726//F
CLB_R15C9.F1 net 1.305R I2/N$2726//F
CLB_R15C9.X Tilo 1.300R I2/CLCO//G
I2/CLCO//G
CLB_R19C7.F2 net 2.735R I2/CLCO//G
CLB_R19C7.X Tilo 1.300R I2/NENBEXT//G
I2/NENBEXT//G
TBUF_R12C2.2.T net 21.792R I2/NENBEXT//G
TBUF_R12C2.2.O Ton 0.800R I2/TBUF_JH_2
P31.O net 26.416R I2/DATIN1<4>
P31.PAD Tops 5.060R I2/DAT<4>
I2/DAT<4>.OUTBUF
I2/DAT<4>
-------------------------------------------------
Total (15.4% logic, 84.6% route) 71.159ns
--------------------------------------------------------------------------------
Delay: 68.708ns I0/NPD00 to I2/DAT<4>
Path I0/NPD00 to I2/DAT<4> contains 5 levels of logic:
Path starting from Comp: P27.PAD
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
P27.I1 Tpid 1.180R I0/NPD00
I0/NPD00
I0/NPDB00
CLB_R14C9.F4 net 6.560R I0/NPDB00
CLB_R14C9.X Tilo 1.300R I2/N$1907//G
I2/N$1907//G
CLB_R19C7.F1 net 4.300R I2/N$1907//G
CLB_R19C7.X Tilo 1.300R I2/NENBEXT//G
I2/NENBEXT//G
TBUF_R12C2.2.T net 21.792R I2/NENBEXT//G
TBUF_R12C2.2.O Ton 0.800R I2/TBUF_JH_2
P31.O net 26.416R I2/DATIN1<4>
P31.PAD Tops 5.060R I2/DAT<4>
I2/DAT<4>.OUTBUF
I2/DAT<4>
-------------------------------------------------
Total (14.0% logic, 86.0% route) 68.708ns
NOTE: The R on the delays refers to Rising.
End of Record #2742 - Last Modified: 09/30/97 14:50 | 
