Answers Database
VERILOG-XL: SDFA Error: Could not find path IN0 to OUT in instance ""
Record #2750
Product Family: Software
Product Line: Cadence
Product Part: Verilog-XL
Problem Title:
VERILOG-XL: SDFA Error: Could not find path IN0 to OUT in instance ""
Problem Description:
Urgency: Standard
Upon doing a timing simulation in Verilog-XL, you may receive the
following errors if you also use the +delay_mode_unit option:
time_sim.sdf L18: SDFA Error: Could not find path IN to OUT in instance ""
time_sim.sdf L183: SDFA Error: Could not find path CTL to OUT in instance ""
time_sim.sdf L281: SDFA Error: Could not find path ADR0 to OUT in instance ""
time_sim.sdf L295: SDFA Error: Failed to find WIDTH timingcheck
time_sim.sdf L297: SDFA Error: Failed to find SETUP timingcheck
You may not use the +delay_mode_unit option while also doing a
SDF annotation. The SDF (Standard Delay Format) file contains
all the timing information for the design.
Solution 1:
If your goal is to do a simulation with unit delays on a Verilog file
generated to do timing simulation, edit the Verilog file (.v) and
comment out the line that calls the "$sdf_annotate" function
with a double slash (//).
In the file "time_sim.v" generated by NGD2VER in the Xilinx
Alliance tools when doing a Verilog timing simulation, you will find:
initial $sdf_annotate("time_sim.sdf");
Change this to:
// initial $sdf_annotate("time_sim.sdf");
Remember to comment out the "initial" statement associated with
this function call when you comment the sdf_annotate function call.
End of Record #2750 - Last Modified: 06/26/99 14:30 |
