Answers Database
M1: QuickSim functional simulation of a Mentor schematic with instantiated XNF (From Coregen 1.4 or other sources)
Record #2899
Product Family: Software
Product Line: Mentor
Product Part: pld_edif2sim
Product Version: 1.4.
Problem Title:
M1: QuickSim functional simulation of a Mentor schematic with instantiated XNF (From Coregen
1.4 or other sources)
Problem Description:
Urgency: Hot
General Description:
How do I create a QuickSim simulation model for a Mentor schematic that
contains instantiated XNF modules?
The XNF netlist may have come from Coregen 1.4 or other sources producing
XNF netlists meeting the XNF Specification.
Solution 1:
NON-HIERARCHICAL QUICKSIM NETLIST WITHOUT CROSS-PROBING
Having instantiated your XNF modules with the proper FILE properties (set
to <file>.xnf), run the following steps. (Be sure to substitute your
design name for "top_design" and your target device family for "xc4000ex".)
1. pld_men2edif top_design xc4000ex
2. pld_edif2sim top_design.edif top_design_sim xc4000ex -m -eddm
PLD_EDIF2SIM merges the XNF modules into the simulation netlist and (using
NGDBUILD), then write out a simprim simulation model into the component
top_design_sim. This design can then be brought into into QuickSim and
simulated:
3. pld_quicksim top_design_sim
You can alternatively specify the name of the original design for the
target netlist:
2. pld_edif2sim top_design.edif top_design xc4000ex -m -eddm
3. pld_quicksim top_design
In this case, the EDDM model is registered as the default simulation model
for the original design, which allows you to run QuickSim on it directly
after the model is generated.
Solution 2:
HIERARCHICAL QUICKSIM NETLIST WITH CROSS-PROBING
PLD_EDIF2SIM is normally run to obtain a QuickSim simulation model from
EDIF. Unfortunately, this script is only written to output flat EDDM
models (although it can write out hierarchical VHDL and Verilog models).
To use QuickSim with cross-probing effectively, a hierarchical netlist must
be generated.
Having instantiated your XNF modules with the proper FILE properties (set
to <file>.xnf), run the following steps. (Be sure to substitute your
design name for "top_design" and your target device family for "xc4000ex".)
1. pld_men2edif top_design xc4000ex
2. ngdbuild -p xc4000ex top_design.edif top_design_sim.ngd
3. ngd2edif -a -w -v mentor top_design_sim.ngd top_design_sim.edn
4. enread top_design_sim.edn -rcf $LCA/data/enread.cfg -r
Steps 2 through 4 are the steps normally run by PLD_EDIF2SIM without the
options used to generate a flat netlist. These steps write out a simprim
simulation model into the component top_design_sim. This design can then
be brought into into QuickSim and simulated with cross-probing:
5. pld_quicksim -cp top_design_lib/top_design
Note that, in this case, the simulation model is ALWAYS written under
top_design_lib.
End of Record #2899 - Last Modified: 08/31/98 11:02 |
