Answers Database
Timing: How to find the paths not covered by Constraints/Advanced Analysis? i.e. coverage < 100%, i.e. 0 items analyzed
Record #2963
Product Family: Software
Product Line: FPGA Implementation
Product Part: trce
Product Version: 1.3
Problem Title:
Timing: How to find the paths not covered by Constraints/Advanced Analysis? i.e. coverage <
100%, i.e. 0 items analyzed
Problem Description:
Urgency: Standard
General Description: In the constraints covered section of the .twr file,
87.1% (for, example) is covered. How do you find the the 12.9% of
connections not covered?
Solution 1:
One other cause of less than 100% coverage is the missing
connections of any of the Path Tracing Controls (i.e. tbuf_i_o
disabled, reg_sr_q disabled).
Enable the path tracing controls for the set/reset paths
(reg_sr_q) will enable to see all the unconstrained paths.
These paths are disabled by default regardless of the
use of the unconstrained path report.
This is an example that can be done in the PCF file,
enable=reg_sr_q;
enable=reg_sr_clk;
disable=tbuf_i_o;
Enabling the 'Reg_SR_Q' & 'Reg_SR_Clk' path tracing
controls is recommend with design that have a synchronous
element driving a Set/Reset pin. There are other
path tracing controls that can be enabled or disabled
in order to get the coverage of the design closer to 100%.
Also see (Xilinx Solution 6450) about the 'reg_sr_clk' path
tracing controls.
Solution 2:
The percentage of connections covered by timing constraints
is given in a "% coverage" statistic. The statistic does not
indicate the percentage of paths covered; it indicates the
percentage of connections covered.
Even if you have entered constraints that cover all paths in the
design, this percentage may be less than 100%, since some
connections are never included for timing analysis (for
example, connections to the STARTUP component).
Another example is the case where a static pin drives a LUT,
which combines with no other signals and then drives other
logic. This can happen at the start of a carry chain where a
FORCE mode is used from a logic 1 or 0. Also if terms for
carry logic are connected to a CLB, but go unused within
the CLB, these connections will never be traced.
If the user timespecs are incomplete, then he/she may do a
Path Filters->Timing Constraint Filters->Report Paths Not
Covered By Timing constraints.
This will add a default group to the timing report that
covers the unconstrained paths in the design (except for the
connections that are never included, mentioned above).
Solution 3:
The following command will analyze the design.ncd using the timing
constraints in the design.pcf and generate a report called output.twr
which will include delays of all uncovered paths.
trce -u design.ncd design.pcf -o output.twr
Please refer to the Dynatext Browser book titled "Development
System Reference Guide" in Chapter 11 for more information.
Solution 4:
The most common reason for connection coverage not hitting
100% is that elements in the design have TIGs. A TIG on an
element, will cause trace to stop tracing the path, possibly
leaving connections on the "other side" of the element
uncovered. A TIG on a path, on the other hand, will have all
of it's connections accounted for in the coverage statistic.
End of Record #2963 - Last Modified: 10/25/99 14:37 |
