Answers Database
CPLD: How to calculate the timing accross a latch in a 9K device
Record #3006
Product Family: Hardware
Product Line: 9500
Product Part: 9500
Problem Title:
CPLD: How to calculate the timing accross a latch in a 9K device
Problem Description:
Urgency: standard
General Description:
The timing report (design.tim) produced by the CPLD software does
not show timing for any paths accross a latch. What is the correct
way of calculating timing accross a latch?
Solution 1:
Transparent latches are implemented in 9K devices by gating the D
and G inputs into the async CLR and PRE inputs of a D-flip-flop
(FDCP primitive). Hence, the delay calculations would be the same
as when tracing a path through the async clear or preset of a
D-flop.
The logic equations for a 9K latch are:
Q.preset = D * G
Q.clear = /D * G
The pin-to-pin propagation delay for both the data and latch-enable
paths in a 9K device would be calculated as follows, if the D and G
inputs are driven by IBUFs and Q drives an OBUF.
tPROP = tIN + tPTSR + tAOI + tOUT.
The values for tIN, tPTSR, tAOI and tOUT can be found in the data
book and are dependent on the speed grade being used.
If there is any additional logic on the D or G inputs, the logic
would usually require an additional macrocell delay (tF + tLOGI +
tPDI). The only logic that could possibly be implemented in the
same macrocell as the latch (requiring no additional delay) would
be a single AND-gate (any size) on the G path (but not on the D
path).
End of Record #3006 - Last Modified: 12/07/99 10:49 |
