Answers Database
CONCEPT-HDL 13.5: In a mixed-flow, Xilinx primitives are listed in the "resource file" list of Synplify
Record #3029
Product Family: Software
Product Line: Cadence
Product Part: concept
Problem Title:
CONCEPT-HDL 13.5: In a mixed-flow, Xilinx primitives are listed in the "resource file" list
of Synplify
Problem Description:
Urgency: High
General Description:
The Cadence project manager delivered with Concept-HDL 13.5
(and, earlier versions), Iists Xilinx primitives in the "resource file"
list of Synplify in a mixed-flow environment.
Solution 1:
Concept-HDL is integrated with Synplicity's Synplify for design synthesis. In
mixed-level design methodology, Concept-HDL writes Verilog and VHDL
directly from a block diagram schematic. In the PE 13.5, the entire design is
netlisted and passed to Synplify, however, Xilinx primitives are listed in the
"resource file" list of Synplify which conflicts with the synthesis library definition
of the primitive.
There are 2 issues to notice:
1> Synplify is not able to find declarations for the primitives that are in the
schematic Verilog file since Concept-HDL provides them in all lower case.
2> Synplify will synthesis these behavioral models of the primitives.
This is corrected in PE 13.6. In the PE 13.6 release, there will be no netlisting
of these primitives for the purpose of going into Synthesis. This provides for
individual synthesis of the HDL blocks and EDIF netlisting of each of the
schematic blocks, and also the ability to use a previously generated EDIF view
for blocks, rather than requiring a Verilog, VHDL or schematic view.
End of Record #3029 - Last Modified: 06/26/99 10:08 |
