Xilinx Answer #3074 : A1.5/1.4: Cadenece Concept and Verilog-XL: Functional simulation with Mode and Boundary Scan pins in schematic

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A1.5/1.4: Cadenece Concept and Verilog-XL: Functional simulation with Mode and Boundary Scan pins in schematic

Record #3074
Problem Title:
A1.5/1.4: Cadenece Concept and Verilog-XL: Functional simulation with Mode and Boundary Scan pins in schematic

Problem Description:

Urgency: Standard

           possible from Concept schematics using Verilog-XL when Mode
           or Boundary Scan pins are used in the design.

Solution 1:

When concept2xil creates the verilog functional simulation netlist, the
Boundary Scan and Mode pins are not brought out as ports if used in the
schematic design. If a functional simulation is to be performed, it
may be done one of two ways.

1. The output EDIF netlist may be run partially through M1 to create
     a SIMPRIM based simulation which will include the Boundary Scan and
     Mode pins as declared ports. To do this, run the following:

     ngdbuild <design>.edf
     ngd2ver -ul -tf <design>.ngd

     This will create a structural SIMPRIMs-based simulation netlist,
     <design>.v, as well as a template testbench file, <design>.tf, which
     may be modified and used as the design stimulus file. In this case,
     the same testbench file may be used for both functional and timing
     simulation.

2. A functional simulation may be performed on the verilog functional
     simulation netlist created from concept2xil if the testbench file is
     modified so that:

     a) The instantiated concept2xil created functional simulation verilog
        netlist has the Boundary Scan and Mode pins ports omitted from the
        declaration. For example:

      mode_pin uut (.clock (clock), .non_mode_pin (non_mode_pin));

      Notice that no Boundary Scan or Mode pin ports are specified.

     b) All Boundary Scan and Mode Pin signals reference the proper scope
        (ie. design_instance_name.sig_name). For example:

        $monitor("%t",$realtime,, "| %b", clock,, uut.mode0);

        Being displayed is the Mode pin signal mode0 from the instantiated
        instance name uut for the concept2xil verilog netlist.

     c) All Boundary Scan and Mode pin inputs may be driven with the verilog
        "force" command :

        #200 force uut.mode0 = 1;

        Applying a '1' to the Mode pin signal mode0 from the instantiated
        instance name uut for the concept2xil verilog netlist after 200 units.

     Note that for this flow, the testbench for functional and timing
     simulation will be different. These signal references would need
     to be changed back for a timing simulation when these pins will be
     declarded as ports for the post-M1 simulation of the design.

Reference CR# 101576

End of Record #3074 - Last Modified: 01/10/00 20:14

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