Answers Database
CPLD: 9500/XL :How do the BUFGSR, BUFG, OE buffers work on the 9500/XL?
Record #3122
Product Family: Hardware
Product Line: 9500
Product Part: 9500
Problem Title:
CPLD: 9500/XL :How do the BUFGSR, BUFG, OE buffers work on the 9500/XL?
Problem Description:
Urgency: Standard
General Description:
How does the BUFGSR, BUFG, OE work? Do they use dedicated routing?
Does it globally connect to all flops in the design such as on the FPGA's?
How do I connect it? Is there any way to force using global routing?
Solution 1:
The BUFGSR must be manually connected to all the flops the user wants the
signal to go to. This is different than on the FPGA, where using the STARTUP
and connecting to the signal GSR will globally set/reset all flops on the
device.
On the CPLD, BUFGSR will use dedicated routing, if from the buffer to
the flop there is no logic gates or anything else in between them. By doing
this will allow the M1 tools to use the dedicated routing on the device. So
the BUFGSR can be connected to the set or resets of the different flops, and
when this signal is asserted will have the desired affect.
The BUFG and BUFOE buffers work in the same manner.
End of Record #3122 - Last Modified: 12/17/99 14:40 |
