Answers Database
A1.5/1.4: How to import a VHDL, Verilog, or LogiBLOX generated netlist into a Concept schematic
Record #3134
Product Family: Software
Product Line: Cadence
Product Part: concept
Problem Title:
A1.5/1.4: How to import a VHDL, Verilog, or LogiBLOX generated netlist into a Concept
schematic
Problem Description:
Urgency: Standard
General Description: The following is instructions for incorperating a VHDL
or Verilog generated netlist into a Concept schematic for the M1 toolset.
The VHDL or Verilog code must have been already synthesized to an
M1-compatible netlist (XNF, EDIF or NGO) on a seperate synthesis tool.
These instructions also include how to add LogiBLOX components.
Solution 1:
1. Synthesize the module to be instantiated into the Cadence schematic.
If any of the ports are to be connected to logic in the schematic,
besure not to insert I/O buffers on these ports when synthesizing.
Refer to the synthesis tool's instructions for properly creating a
sub-module.
If this is a LogiBLOX module, create a Verilog or VHDL simulation
netlist and use this netlist along with the produces NGO file for
the remainder of the instructions.
2. Create a Cadence Concept project directory.
3. Copy the VHDL or Verilog file with the produced netlist file
(XNF, EDIF, or NGO) to the project directory.
4. Invoke Concept.
5. Enter the following command in the Concept message window in order
to create the symbol for the netlist to place into the schematic:
For a Verilog netlist, enter the following command:
genview -i <verilog_filename> -v logic body verilog
For a VHDL netlist, enter the following two commands:
genview -i <vhdl_filename> body vhdl
genview -i <vhdl_filename> -v logic verilog vhdl
After these commands are run, a sub-directory is created in which
contains the symbol and logic information. The name of this sub-directory
is the same name as the module name for the Verilog file or the entity
name for the VHDL file. Edit the verilog.v file in the
<new_symbol_name>/logic directory adding the following line after the
module declaration :
parameter cds_action = "ignore";
For example, from a UNIX prompt type:
vi <module_or_entity_name>/logic/verilog.v
You may use a different text editor if you choose. Vi is just used as
an example.
Then edit the file adding the new parameter line:
module my_alu (data_out, data_in, control, clock);
parameter cds_action = "ignore";
input clock;
input [3:0] control;
...
...
endmodule
6. Add the genview created symbol to the Concept schematic and connect it
accordingly to your schematic.
7. Once the schematic is completed, run concept2xil on the design :
concept2xil -family <device_family> <top_level_design_name>
Concept2xil will create a sub-directory defaultly called xilinx.run
in which it has placed an EDIF file, <design>.edf, if it does not
encounter any errors with the design.
8. Copy the netlist file (XNF, EDIF, or NGO) into the implementation
directory.
9. Implement the design in M1.
End of Record #3134 - Last Modified: 06/30/98 11:27 |
