Answers Database
TAENGINE M1.3: ERROR:hi402 there is no original clock signal to clock pin *.CLKF
Record #3142
Product Family: Software
Product Line: CPLD Implementation
Product Part: taengine
Product Version: 1.3
Problem Title:
TAENGINE M1.3: ERROR:hi402 there is no original clock signal to clock pin *.CLKF
Problem Description:
Urgency: standard
General Description:
Customer has a cpld design that they want to produce timing sim data for. In m1.3 the design will t
ranslate and fit with no problems. But then the taengine is executed and right away the flow engine
stops and the design manager will report that the deign was timed with errors. If you open the tim
ing report it is blank. The last line of the fe.log is :
taengine -f design -l design.tim
Solution 1:
This error has been found in the M13.7 release with all the latest patches, however the problem has
been fixed in the M1.4
release.
End of Record #3142 - Last Modified: 03/09/98 14:59 |
