Answers Database
CONCEPT-HDL 13.5: User defined constraints are not passed from the schematic to Synplify
Record #3193
Product Family: Software
Product Line: Cadence
Product Part: concept
Problem Title:
CONCEPT-HDL 13.5: User defined constraints are not passed from the schematic to Synplify
Problem Description:
Urgency: High
General Description:
Concept-HDL 13.5 (and, earlier versions) does not pass constraints
entered in the schematic to Synplify. The EDIF netlist synthesized
from Synplify which the Xilinx Alliance tools reads will not have Xilinx
constraints.
For example: If an user enters a RLOC constraints on a FDCE, this
information would be lost.
Solution 1:
Concept-HDL is integrated with Synplicity's Synplify for design synthesis. In
mixed-level design methodology, Concept-HDL writes Verilog and VHDL
directly from a block diagram schematic. In the PE 13.5, the entire design is
netlisted and passed to Synplify, however, constraints were lost in the translation
from the schematic to the HDL file for synthesis.
This is corrected in PE 13.6. In the PE 13.6 release, the schematic properties
would be passed to P&R, but Synthesis constraints would have to be added to
the HDL or provided to Synplify via the Synplify Constraints editor. This provides
for individual synthesis of the HDL blocks and EDIF netlisting of each of the
schematic blocks, and also the ability to use a previously generated EDIF view
for blocks, rather than requiring a Verilog, VHDL or schematic view.
End of Record #3193 - Last Modified: 06/24/99 13:40 |
