Answers Database
M1.4 Core Tools - All M1.4 bug fixes available in M1.4 Core Tools Patch on the Xilinx Download Area.
Record #3248
Product Family: Software
Product Line: Merged Core
Product Part: general
Problem Title:
M1.4 Core Tools - All M1.4 bug fixes available in M1.4 Core Tools Patch on the Xilinx
Download Area.
Problem Description:
The latest M1.4 Core Tools Patch containing all fixes mentioned
below is available on the Xilinx Download Area:
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt17.zip
Each new Core Tools Update contains all fixes included in previous updates.
The following issues are fixed in the latest M1.4 Core Tools Patch on the Xilinx Download Area.
New fixes added by Core Tools Patch #17:
Fixes map fatal error:
FATAL_ERROR:x4kma:x4kmagrclapse.c:1001:1.90.12.8 - No
route-thru available in pack_lutflop() to swap with H
input pin 8:
http://www.xilinx.com/techdocs/4459.htm
New fixes added by Core Tools Patch #16:
Adds environment variable XIL_TOSS_INVALID_CLBMAPS to
allow map to ignore invalid CLB Maps.
http://www.xilinx.com/techdocs/4373.htm
Fixes 4kxl map crash.
http://www.xilinx.com/techdocs/4374.htm
Fix for map corruption of 4kxl CLB logic.
http://www.xilinx.com/techdocs/4248.htm
Fix for HP only 4kxl PAR crash.
http://www.xilinx.com/techdocs/4294.htm
New fixes added by Core Tools Patch #15:
Fixes problem where bitgen with tie down leaves unused IOBs
floating in 4k devices.
http://www.xilinx.com/techdocs/4309.htm
Fixes problem where bitgen with tie down crashes on PCs only
for a paticular 5200 case.
http://www.xilinx.com/techdocs/4310.htm
Fixes problem where bitgen crashes for a particular 4kxl case.
http://www.xilinx.com/techdocs/4160.htm
Fixes problem where bitgen with tie down leads to IOBs being
incorrectly tri-stated in 4kxl devices.
http://www.xilinx.com/techdocs/4253.htm
Fixes problem where lca2ncd handles certain XACT route-thrus
incorrectly leading to drc warnings.
http://www.xilinx.com/techdocs/4311.htm
Fixes problem where lca2ncd converts certain XACT route-thrus
into CLB configurations that will lead to drc errors if a re-entrant
route is performed using PAR.
http://www.xilinx.com/techdocs/4312.htm
New fixes added by Core Tools Patch #14:
Fixes problem where TNMs were not being attached to all FFS.
http://www.xilinx.com/techdocs/4001.htm
Fixes problem where map was unable to follow RLOC constraints
on RAM. The environment variable XIL_MAP_NO_FMAP_PACK must
also be set for this bug fix to work.
http://www.xilinx.com/techdocs/4026.htm
Fixes map fatal error:
FATAL_ERROR:x4kma:x4kmacarry.c:2842:1.122.12.8 -
Illegal call to swap. Cannot move RAM to G because H1 pin
is not free: I164/oh_we_reg/$1I13.
http://www.xilinx.com/techdocs/4080.htm
Fixes map fatal error:
FATAL_ERROR:x4kma:x4kmawritengd.c:82:1.17 - F-LUT physonly
route-thru for CINsig in CLB: WZERO does not drive the X,
QX or QY pin.
http://www.xilinx.com/techdocs/4025.htm
Fixes map problem where input signal driving two paths is
corrupted by map.
http://www.xilinx.com/techdocs/4082.htm
New fixes added by Core Tools Patch #13:
Fixes map problem where Map creates TIMEGRPs in PCF file
that are incorrect.
http://www.xilinx.com/techdocs/4060.htm
Fixes map error:
ERROR:baste:117 - RLOC_ORIGIN value of "R8C0" on TBUF32
symbol "tbzero", when added to the RLOC values, does not
correspond to a valid site name.
http://www.xilinx.com/techdocs/4061.htm
New fixes added by Core Tools Patch #12:
Fixes map fatal error:
FATAL_ERROR:x4kmamerge.c:2858:1.145.12.11 -
Too many signals to move and not enough slots
on comp ...
http://www.xilinx.com/techdocs/3843.htm
Fixes map corruption problem where CLB is
configured with wrong LUT driving D-input
of flop.
http://www.xilinx.com/techdocs/3875.htm
Fixes map fatal error related to use of
5-input EQN in 5200 device:
FATAL_ERROR:baste:basteparse.c:333:1.1 -
Unable to find signal name in mlparse: CI.
http://www.xilinx.com/techdocs/3876.htm
Fixes FATAL_ERROR:baste:bastetspec.c:908:1.69 -
No pins of NC_SIGNAL ...
http://www.xilinx.com/techdocs/3877.htm
Fixes Guided Map crash.
http://www.xilinx.com/techdocs/3822.htm
Fixes FATAL_ERROR:baste:bastetspec.c:982:1.69.14.2 -
NC_BEL ECL_IN_2BIT is not connected to NC_SIGNAL ...
http://www.xilinx.com/techdocs/3879.htm
Fixes High Density Placer crash PAR.
http://www.xilinx.com/techdocs/3880.htm
New fixes added by Core Tools Patch #11:
Adds environment variable XIL_MAP_TOLERATE_TIG_ERROR
that changes fatal error to non-fatal warning when
map drops a TIG.
http://www.xilinx.com/techdocs/3810.htm
Fixes Fatal Error:baste:bastetspec.c:1333:1.69
http://www.xilinx.com/techdocs/3811.htm
Allows Turns Engine to use node names with "-"
and "_" charachters.
http://www.xilinx.com/techdocs/3812.htm
Adds environment variable CM_EXCLUDE_XQYQ that
prevents PAR from using output to output route-thrus
using flops.
http://www.xilinx.com/techdocs/3813.htm
Fixes PAR crash in placement.
http://www.xilinx.com/techdocs/3814.htm
Fixes map problem that lead to ngdanno error:
INTERNAL_ERROR:basnb:basnbconv.c:546:1.21
http://www.xilinx.com/techdocs/3815.htm
New fixes added by Core Tools Patch #10:
Fixes FATAL ERROR:basnc:basncsignal.c:262:1.662 -
Could not find a bel...
http://www.xilinx.com/techdocs/3760.htm
Fixes problem where map loses external feedback
connection for a CLB.
http://www.xilinx.com/techdocs/3761.htm
Fixes problem where par creates illegal route-thru
in Clock IOB.
http://www.xilinx.com/techdocs/3742.htm
Fixes mapping error where 5200 readback symbol is
improperly connected. The RIP pin of the READBACK
symbol is used instead of DATA.
http://www.xilinx.com/techdocs/3772.htm
New fixes added by Core Tools Patch #9:
Fix for map problem where corrupted clock buffer
connectivity results in PAR crash.
http://www.xilinx.com/techdocs/3396.htm
Fix for 5200 map problem where an inversion is dropped
between latch and and2b2 symbol.
http://www.xilinx.com/techdocs/3722.htm
Map crashes with segmentation fault for a particular case.
http://www.xilinx.com/techdocs/3723.htm
Fixes map FATAL_ERROR:baste:bastetspec.c:1333:1.69
TNM TI_H1 on NET 'TI_H1' has a reference that has
no NC_BEL and no TECHMAP_SIGNAL
http://www.xilinx.com/techdocs/3632.htm
Map crashes for a particular case.
http://www.xilinx.com/techdocs/3661.htm
Fixes Map FATAL_ERROR:x4kma:x4kmamerge.c:4429:1.145.12.5 -
Missing signal on pin 10.
http://www.xilinx.com/techdocs/3655.htm
Fixes Map FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins
of NC_SIGNAL ...
http://www.xilinx.com/techdocs/3724.htm
Fixes Map FATAL_ERROR:x4kma:x4kmamerge.c:1561:1.145.12.7 -
No flop rt available.
http://www.xilinx.com/techdocs/3725.htm
Fixes Map corruption during logic replication that lose
HLUT connection.
http://www.xilinx.com/techdocs/3726.htm
Fixes bitgen failure during Tiedown.
http://www.xilinx.com/techdocs/3727.htm
New fixes added by Core Tools Patch #8:
Fix for Fatal_error:x3kma:x3kmarmunused.c:120:1.8
http://www.xilinx.com/techdocs/3597.htm
Fix for Fatal_Error:x4kma:x4kmacarry.c:2946:1.130 -
Illegal call to swap...
http://www.xilinx.com/techdocs/3662.htm
Fix for map problem where back annotated simulation
data is incorrect.
http://www.xilinx.com/techdocs/3663.htm
Fix for FATAL_ERROR:baste:bastetspec.c:1737:1.69
http://www.xilinx.com/techdocs/3664.htm
Fix for FATAL_ERROR:x4kma:x4kmamerge.c:1384:1.120.10.4 -
Tried to move a signal to an occupied pin on comp...
http://www.xilinx.com/techdocs/3665.htm
Fix for bitstream problems related to OMUX2 usage.
http://www.xilinx.com/techdocs/3666.htm
New fixes added by Core Tools Patch #7:
Map fix to handle greater than 64K.
http://www.xilinx.com/techdocs/3616.htm
Map fix for a 5200 crash.
http://www.xilinx.com/techdocs/3617.htm
Map enhancement to add BUFGP/S support to floorplanner.
http://www.xilinx.com/techdocs/3618.htm
The Template Manager has been fixed to correct problem
where customized template options are lost when other
template changes are made.
http://www.xilinx.com/techdocs/3588.htm
Fix for dc2ncf problem where set_output_delay command
incorrectly affects any following set_max_delay commands.
http://www.xilinx.com/techdocs/3619.htm
New fixes added by Core Tools Patch #6:
PAR introduces a DRC error:
ERROR:x45dr - netcheck: Signal <net> is routed to the
O pin of block <comp> on routing which is not available
because the EC pin is using the Logic Zero option.
http://www.xilinx.com/techdocs/3570.htm
New fixes added by Core Tools Patch #5:
Map FATAL_ERROR:x4kma:x4kmagrclapse.c:1953:1.90.12.2 -
No pin for sig...
http://www.xilinx.com/techdocs/3385.htm
Map Fixes FATAL_ERROR:baste:bastetspec.c:908:1.69
No pins of NC_SIGNAL <signal name> belong to ...
http://www.xilinx.com/techdocs/3474.htm
Map FATAL_ERROR:x4ema:x4emaclb.c:663:1.44:5.2 - Flop in Y found
http://www.xilinx.com/techdocs/3381.htm
Map FATAL_ERROR:x4kma:x4kmamerge.c:2460:1.145
http://www.xilinx.com/techdocs/3379.htm
Map fails to trim redundent reset/preset signals.
http://www.xilinx.com/techdocs/3525.htm
Map crash during optimizing phase.
http://www.xilinx.com/techdocs/3526.htm
Map FATAL_ERROR:basnc:basncsignal.c:262:1.62 -
Could not find a bel for a signal...
http://www.xilinx.com/techdocs/3527.htm
PAR core dumps during placement of large 4000xv design.
http://www.xilinx.com/techdocs/3528.htm
Ngdanno updated to handle new CB228 pkgs for 4kxl devices.
http://www.xilinx.com/techdocs/3529.htm
Ngdanno fix to allow back annotation to logical model
for a case not covered.
http://www.xilinx.com/techdocs/3530.htm
New fixes added by Core Tools Patch #4:
MAP FATAL ERROR: Illegal situation for H1 pack.
http://www.xilinx.com/techdocs/3447.htm
Map corrupts logic leading to DRC message:
WARNING:x4kdr:82 - Blockcheck: The pin "F2"
on comp (mapped physical logic cell) "XXX"
is configured to be used but has no signal
attached to it.
http://www.xilinx.com/techdocs/3357.htm
Map crash.
http://www.xilinx.com/techdocs/3448.htm
FATAL_ERROR:basnc:basncsignal.c:262:1.62
Could not find a bel for a signal on pin IK of comp <XXX>.
http://www.xilinx.com/techdocs/3449.htm
ERROR:x4kma:312 - The following symbols
could not be constrained to a single CLB.
http://www.xilinx.com/techdocs/3450.htm
Map gives no trim report if a fatal error has occured.
http://www.xilinx.com/techdocs/3451.htm
FATAL_ERROR: baste:bastecomp.c:1943:1.61.9.3 -
idx not found.
http://www.xilinx.com/techdocs/3452.htm
Ngdanno has problem with non-numeric pins.
http://www.xilinx.com/techdocs/3455.htm
PAR core dump on xc5200 design.
http://www.xilinx.com/techdocs/3456.htm
PAR uses route-thrus on bonded pads for
xc3000 and xc5200 devices.
http://www.xilinx.com/techdocs/3457.htm
Xnf2ngd fails for very attribute values.
This has been seen with both long EQN attributes
and TNN attributes.
http://www.xilinx.com/techdocs/2934.htm
Map core dump on floor planned design.
http://www.xilinx.com/techdocs/3458.htm
Ngdanno problem with back annotation of EQN symbol timing.
http://www.xilinx.com/techdocs/3459.htm
Ngdanno problem with back annotation to logical model.
http://www.xilinx.com/techdocs/3460.htm
PAR runs out of memory on a case with routed hard macros (.nmc's).
http://www.xilinx.com/techdocs/3461.htm
PAR crash on xc5200 design.
http://www.xilinx.com/techdocs/3462.htm
PAR hangs when single component hard macros are
located using a .pcf constraint.
http://www.xilinx.com/techdocs/3463.htm
New fixes added by Core Tools Patch #3:
Optimization of OFDT symbol results in dangling tri-state control pin.
http://www.xilinx.com/techdocs/3311.htm
ERROR:baste:262 - Bad format for LOC constraint. Customer ran into
constraint size limitation assigning multiple sites to pin LOCs
trying to perform the equivalent of an edge constraint.
http://www.xilinx.com/techdocs/3312.htm
Map crashes trying to push buffer/inverter into hard macro (.nmc).
http://www.xilinx.com/techdocs/3314.htm
Ngdanno annotates delays for DP RAM produce sim results inconsistent
with TRCE.
http://www.xilinx.com/techdocs/3315.htm
PAR fails with Arithmatic Exception error on hard macro design.
http://www.xilinx.com/techdocs/3316.htm
PAR core dumps during Initial Timing Analysis.
http://www.xilinx.com/techdocs/3317.htm
New fixes added by Core Tools Patch #2:
Timespec'ing RAMS (dualport) to FFS only covers SPO path.
http://www.xilinx.com/techdocs/3243.htm
FATAL_ERROR:x4kma:x4kmamerge.c:1879:1.145 - CIN signal
is not on input pin of F or G LUT of ...
http://www.xilinx.com/techdocs/3244.htm
ERROR:x4kma:312 - The following symbols could not be
constrained to a single CLB: RAM16X1S symbol <instance name>
(output signal=<net name>) FDCE symbol <instance name>
http://www.xilinx.com/techdocs/3245.htm
FATAL_ERROR:x4kma:x4kmamerge.c:2585:1.145.12.2 - Too
many signals and not enough slots on comp <instance name>.
http://www.xilinx.com/techdocs/3246.htm
FATAL_ERROR:baste:bastecomp.c:564:1.72 - Moving BEL from
U7451 to occupied belsite 1 in <instance name>
http://www.xilinx.com/techdocs/3247.htm
FATAL_ERROR:x4kma:x4kmacarry.c:2703:1.122 - Illegal call to swap
Cannot swap if SR pin and F is driving H-LUT <instance name>.
http://www.xilinx.com/techdocs/3250.htm
Mapper fails with Application Fault on EX and XL Devices on PC only.
http://www.xilinx.com/techdocs/3251.htm
Solution 1:
The latest M1.4 Core Tools Patch containing all fixes mentioned
above is available on the Xilinx Download Area:
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt17.zip
Win95 Users should re-install the Win95 performance patch
after installing the latest Core Tools Patch.
Reference: http://www.xilinx.com/techdocs/3509.htm
End of Record #3248 - Last Modified: 05/11/99 14:45 |
