Answers Database
CPLD M1.3(patch),M1.4: Pin location assignments for 9500 designs are not seen
Record #3275
Product Family: Software
Product Line: CPLD Implementation
Product Part: hitop
Product Version: 1.4
Problem Title:
CPLD M1.3(patch),M1.4: Pin location assignments for 9500 designs are not seen
Problem Description:
Urgency: Standard
General Description: Pin assignments may not seen by the CPLD fitter if:
1)pin assignments are made in the .ucf file.
2)pin assignments are made in abel design.
3)pin assignments are made in a schematic sheet other than the top level
Solution 1:
This problem was introduced by one of the M1.3 patches and
carried through to M1.4.
The current work around is to assign pin locations in a
guide(.gyd) file.
For using a guide file see (Xilinx Solution 2719).
For schematic designs, assign pin location on the top level schematic.
Solution 2:
A patch is now available on the Xilinx Download area at:
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_sol10_m14.tar.Z - for Solaris
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_sun10_m14.tar.Z - For SunOS
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_hp10_m14.tar.Z - For Hp-UX
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_nt10_m14.zip - For Win'95/NT
These update files also include the changes from previous cpld updates.
All zip files are created using WinZip. To obtain this utility,
access WinZip's web site at http://www.winzip.com
Solution 3:
The M1.4 patch does not resolve a known issue where macro I/O
cells are instantiated in the design (IPAD4, IBUF4) and the LOC
constraints are contained in a UCF file.
For this case, splitting the I/O into individual primitives
(IPAD, IBUF) is one alternative. The other is to use the GYD file.
End of Record #3275 - Last Modified: 08/26/98 16:57 |
