Answers Database


CPLD: What are negative setup times in CPLD Performance report?


Record #3302

Product Family: Software

Product Line: M1 Graphical/General

Product Part: Design Manager

Product Version: 1.3

Problem Title:
CPLD: What are negative setup times in CPLD Performance report?


Problem Description:

Urgency:   Standard

General Description:
After running M1 and creating a 'Post Layout Timing Report',
in the timing report (a.k.a. Performance Summary Report),
there may be negative values for setup times such as below:

Setup to Clock at the Pad (tSU) 	  :	   -13.0ns (0 macrocell levels)
Data signal 'CS10' to TFF D input Pin at '&__A__55.D'
Clock pad 'R_W' 						  (Global Clock)

Negative setup time is the result of a clock signal that is
slower than the total delay and setup on the data input to
the ff. Normal (positive) setup time is when the ff data
must be stable before clock comes. The equation to calculate
the time is:

Tsu=Tin+Tlogi+Tsui-Tgck

In the case where setup time is negative, the data arrives
at the ff, stays for setup, then disappears before the clock
comes. In the above equation, Tgck is larger than the sum of
the rest, therefore there is a negative Tsu.

For more information on this or equations for other configurations,
please see the Xilinx App note XAPP071 - Using the XC9500 Timing
Model. http://www.xilinx.com/xapp/xapp071.pdf


Solution 1:

To resolve the timing problem, the data must be maintained on the
input of the ff until clock comes (Tgck). The negative Tsu is the
additional time the data must remain valid before the clock comes.





End of Record #3302 - Last Modified: 01/03/00 13:45

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!