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NGDBUILD: "logical block ' ' of type 'READBACK' is unexpanded" with a Synplify netlist
Record #3595
Problem Title:
NGDBUILD: "logical block ' ' of type 'READBACK' is unexpanded" with a Synplify netlist
Problem Description:
Urgency: Standard
General Description: Ngdbuild issues a warning on the instantiated
READBACK component in your HDL:
warning basnu:93-logical block 'rebk1' of type 'READBACK' is unexpanded.
Solution 1:
Synplicity's synplify incorrectly declares the READBACK symbol in
the xc4000 libraries. The READBACK component is actually composed
of 2 components: 1 RDBK and 1 RDCLK. If these 2 components are
declared instead of READBACK, the design will be able to translate
through ngdbuild. Another solution to the problem is by changing
the file extension from .xnf to .sxnf. This performs a translation
step of Synopsys understood components. Synplify borrows these
Synopsys component names. So there are 2 work-arounds:
1> declare RDBK and RDCLK
OR,
2> change .xnf to .sxnf or .edf to sedif
Note: Instantiating the RDCLK indicates to the FPGA that the USER
clock will be used for readback. If this is not the case, then only
instantion of the RDBK is necessary, and the FPGA will use the
onboard CCLK for readback.
Solution 2:
// XC4000e/ex/xl - READBACK Verilog code
`include "/path/to/synplify/lib/xilinx/xc4000.v"
module rdbk_ex (rt, clk, rd, rip_p);
input rt, clk;
output rd, rip_p;
RDBK U0 (.TRIG (rt), .DATA (rd), .RIP (rip_p));
RDCLK U1 (.I (clk));
endmodule
Solution 3:
-- XC4000e/ex/xl - READBACK VHDL code
library IEEE;
use IEEE.std_logic_1164.all;
library xc4000;
use xc4000.components.all;
entity rdbk_ex is
port (
rt, clk : in STD_LOGIC;
rd, rip_p : out STD_LOGIC
);
end rdbk_ex;
architecture xilinx of rdbk_ex is
begin
U0: RDBK port map (TRIG => rt, DATA => rd, RIP => rip_p);
U1: RDCLK port map (I => clk);
end xilinx;
End of Record #3595 - Last Modified: 02/03/99 12:06 |
