Answers Database


CONCEPT: How to LOC global buffers in Concept schematic for the XC4000 family?


Record #3693

Product Family: Software

Product Line: Cadence

Product Part: concept

Problem Title:
CONCEPT: How to LOC global buffers in Concept schematic for the XC4000 family?


Problem Description:
Urgency: Standard

General Description: When placing a LOC attribute to locate a
global buffer to a pin location in a Cadence Concept schematic,
Map may issue a similar error to the following:

ERROR:baste:263 - The LOC constraint "BUFG_NNW,BUFGE_NNW,BUFGLS_NNW"
   (a BUFG location) is not valid for bufgls symbol "page1$i1" (output
   signal=unnamed_1_bufgls_i1_o), which is being mapped to the following
   site types:
            BUFGLS

This is due to a probelm with Map correctly translating the pin
number (P10 for instance) to a physical buffer name (such as BUFG_NNW).

Refernce CR# 104386


Solution 1:


To get around this problem, the pin location may be specified either
within the UCF file, for example:

NET <port> LOC=<pin_number>;

where the designer should replace <port> with the name placed on the
wire in between the PAD and buffer or register and <pin_number> with
the dedicated global buffer pin name.

Another option is to specify the location within the schematic using
the quadrant name or physical buffer name.

The following chart lists the quadrant and physical names for each
buffer:

==============================================================
||	Buffer Name    ||	    ||			    ||
|| 4K EX/XL/XV |  4KE  ||  Quadrant || Physical Buffer Name ||
||=============|=======||===========||======================||
||    GCK1     | PGCK1 ||    TL     ||	  <buffer>_WNW	    ||
||-------------|-------||-----------||----------------------||
||    GCK2     | SGCK2 ||    BL     ||	  <buffer>_WSW	    ||
||-------------|-------||-----------||----------------------||
||    GCK3     | PGCK2 ||    BL     ||	  <buffer>_SSW	    ||
||-------------|-------||-----------||----------------------||
||    GCK4     | SGCK3 ||    BR     ||	  <buffer>_SSE	    ||
||-------------|-------||-----------||----------------------||
||    GCK5     | PGCK3 ||    BR     ||	  <buffer>_ESE	    ||
||-------------|-------||-----------||----------------------||
||    GCK6     | SGCK4 ||    TR     ||	  <buffer>_ENE	    ||
||-------------|-------||-----------||----------------------||
||    GCK7     | PGCK4 ||    TR     ||	  <buffer>_NNE	    ||
||-------------|-------||-----------||----------------------||
||    GCK8     | SGCK1 ||    TL     ||	  <buffer>_NNW	    ||
==============================================================

Note: Above replace <buffer> with the type of buffer being used
       (ie. BUFGLS, BUFGE, BUFGP, etc.)

Simply attach the appropriate quadrant or physical location name
to the BUFG in the schematic to specify the location constraint.

For example:

LOC=TL - This specifies to use either GCK1 or GCK8
(for XC4000 EX/XL/XV designs) or SGCK1 or PGCK1
(for XC4000E designs) depending on whether a BUFGP or BUFGS
is being used.

LOC=BUFGLS_NNE - This specifies to use GCK7 for an
XC4000 EX/XL/XV design.

The corresponding pin numbers for each GCK, SGCK, or PGCK can
be found in the pin out listing for the target device within
the Xilinx Data Book.

This problem has been fixed in the 1.5 version of the software.





End of Record #3693 - Last Modified: 09/03/99 10:23

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