Answers Database
FPGA Configuration: XC4000XL internal signal stuck LOW.
Record #3703
Product Family: Hardware
Product Line: 4000XL
Product Part: 4000XL
Problem Title:
FPGA Configuration: XC4000XL internal signal stuck LOW.
Problem Description:
Urgency: Hot
General Description:
***This is Fixed for M1.5 patched in M1.4.***
This applies to the following devices only: xc4002Xl, xc4005XL, xc4010XL. An internal signal seems
to be stuck at a logic LOW even though it's driving source is free to toggle.
Solution 1:
This is due to a defect in the M1.4 data files for the above mentioned parts that allows the utiliza
tion of a path that doesn't exist. The data files are being fixed and this solution record will be
updated when the S/W patch is available.
Work around:
This problem only ocurrs when either of the FastCLK Buffers are used (BUFF_NE and BUFF_SE) as route
throughs by par. To aviod this improper utilization these sites must be prohibited. This solution
describes how to prohibit the sites with constraints while Resolution 2 describes how to manually fi
x this in Epic Design Editor.
Prohibiting BUFF site in a pcf file:
THIS RESOLUTION IS UNDER EVALUATION...
Solution 2:
This problem has been corrected in a combined bitgen and
speed file upgrade:
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/spd_4kxl3_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/spd_4kxl3_m14.zip
Both files contain the same data.
Solution 3:
Removing BUFF route-thru in Epic.
In the Epic Design Editor:
1. Select the signal name that is routed through the BUFF_NE or BUFF_SE site in the Epic List.
2. Click on "Unroute".
3. Select the BUFF in the main window (click to highlight comp).
4. Click on "Add".
5. Either except name in dialogue box or rename comp and click OK.
6. Again select the net in the Epic List.
7. Click on "Autoroute".
8. Again select the BUFF comp.
9. Click on "delete".
10. Save ncd file and exit.
End of Record #3703 - Last Modified: 11/18/98 11:05 |
