Answers Database
2.1i, V1.5, V1.4 COREGEN: 4K Synchronous FIFO LogiCORE output is only valid when RE is enabled
Record #3791
Product Family: Software
Product Line: Coregen
Product Part: Coregen
Product Version: 2.1i
Problem Title:
2.1i, V1.5, V1.4 COREGEN: 4K Synchronous FIFO LogiCORE output is only valid when RE is
enabled
Problem Description:
Urgency: standard
General Description:
The COREGEN 4K Synchronous FIFO data output does not behave the way some
users may expect when RE (READ Enable) is inactive and the FIFO is FULL.
The output is actually only valid when RE is enabled.
After all memory locations in the COREGen FIFO are filled and
the FULL status output goes High, if WE is still asserted on
the next clock cycle, the FIFO output displays the value that
was written to it at the first memory location, even though
the RE (READ ENABLE) input was never asserted.
Solution 1:
After all memory locations in the COREGen FIFO are filled and
the FULL status output goes High, if WE is still asserted on
the next clock cycle, the FIFO output displays the value that
was written to it at the first memory location, even though
the RE (READ ENABLE) input was never asserted.
Again, the FIFO outputs are not guaranteed once RE is
deasserted. If you wish to have the last valid output read
from the FIFO persist over more than one clock cycle,
register the FIFO output, and use the RE signal to control
the CE of this additional register.
Solution 2:
The main aspect of the FIFO's behavior that may be
unexpected is the fact that the FIFO only shows valid
output when RE (Read Enable) is active. Once RE is disabled,
the output can still change at random, even if you are not
doing a READ operation.
The CORE Generator RAM-based FIFO was designed to minimize
the number of clock cycles required to write valid data to,
or read valid data out of, this buffer. Internally there is
a Write Counter that points to the address of the next
writable address in the buffer, and a Read Counter, which
points to the next address location to be read.
In a Single Port RAM-based FIFO, a mux selects either the
Write Counter or the Read Counter to provide the address to
the memory. The RE input acts as the mux select control
signal. The WRITE Counter always points to the next memory
location to be written to, to allow the fastest possible
WRITE operation.
Once the last FIFO memory location has been written to, the
FIFO is now FULL, and the WRITE Counter cycles back to the
first memory location. The value stored at this location
appears at the output of the FIFO even though RE is not
asserted, because the WRITE Counter is providing the
address to the memory (this is because RE is not asserted).
If WE is still enabled on the next clock cycle, the current
contents of the next location will appear at the FIFO output.
Of course, the information at this location will not be
overwritten, because the FIFO is now FULL.
Since RE has not been asserted, you should not care what the
FIFO output is at that point. If you subsequently assert RE,
you should still see the same value at the output. If it is important
that the Read output persist beyond when RE is active, you
must add an output register to the FIFO output and tie the
register's clock enable to RE.
In the case of a Dual Port RAM-based FIFO, there is no mux
selecting between the Write and Read Counters. The output
of the FIFO always reflects the content of the address
on the output of the Read Counter. However, the same
principle about the output of the FIFO being valid only
when RE is active still applies.
End of Record #3791 - Last Modified: 01/26/00 16:27 |
