Answers Database
Coregen v1.4: Exemplar flow (with and without LogiBLOX) (basnb:79 - Pin mismatch, basnu:93 - Unexpanded...).
Record #3947
Product Family: Software
Product Line: Coregen
Product Part: Coregen
Product Version: c1_4
Problem Title:
Coregen v1.4: Exemplar flow (with and without LogiBLOX) (basnb:79 - Pin mismatch, basnu:93 -
Unexpanded...).
Problem Description:
Urgency: Standard
Problem Description:
While trying to incorporate Coregen modules in a synthesis
design using Exemplar, errors similar to the following may be
encountered:
ERROR:basnb:79 - Pin mismatch between block "instance", TYPE="module", and
file "F:\Leonardo\190248\xproj1\ver1\module.ngo" at pin "input(0)". Please
make sure that all pins on the instantiated component match pins in the
lower-level design block. (Pin-name matching is case-insensitive.)
ERROR:basnb:22 - One or more errors were found during design expansion.
Running Logical Design DRC...
WARNING:basnu:93 - logical block "instance" of type "module" is unexpanded.
Logical Design DRC complete with 1 warning(s).
The Exemplar Coregen v1.4 flow is undocumented and not
officially supported. However, this solution record explains
how to make it work.
The main concern is that bus arraying and the bus delimiters
need to be consistent throughout the design. Coregen v1.4
uses XNF-standard angle brackets, while Exemplar uses angle
brackets when exporting XNF only, and parentheses when
exporting EDIF.
Solution 1:
With LogiBLOX.
When LogiBLOX modules are incorporated into the design with
Coregen, the user must use the resolution for "Without
LogiBLOX" within this solution record, in addition to
generating LogiBLOX modules with the same bus delimiter to maintain consistency.
XNF flow
--------
Generate modules using angle brackets as the bus delimiter.
EDIF flow
---------
Generate modules using parentheses as the bus delimiter.
Solution 2:
Without LogiBLOX.
XNF flow
--------
This flow is straight-forward. Coregen generates an XNF
netlist with angle bracket bus delimiters, as does Exemplar.
Nothing additional needs to be done. With Coregen v1.4, this
isthe simplest flow.
EDIF flow
---------
In order to resolve the pin mismatches between the different
bus delimiters, the Coregen XNF must be modified. Using a
text editor, replace all the occurences of angle brackets with
parentheses.
Additionally, bus arraying must be disabled as described by
(Xilinx Solution 3144).
End of Record #3947 - Last Modified: 06/30/98 15:31 |
