Answers Database
SYNPLIFY: How to disable clock buffer (BUFG) insertion?
Record #4084
Product Family: Software
Product Line: Synplicity
Product Part: Synplify
Product Version: 5.0
Problem Title:
SYNPLIFY: How to disable clock buffer (BUFG) insertion?
Problem Description:
Urgency: Standard
General Description: How to disable clock buffer (BUFG) insertion?
By default, Synplify inserts global clock buffers on the clock signals with
the highest fanout. The rules for insertion is defined internally to Synplify,
but typically, Synplify will assign a BUFG to any input signal that directly
drives a clock.
The maximum number of global buffers is defined as 4. Auto insertion of the
BUFG occurs with a fanout threshold of 16 loads.
Solution 1:
Verilog
----------
To turn off automatic clock buffers for entire modules
module my_design (o, i, clk_in) / * synthesis syn_noclockbuf=1 */;
To turn off automatic clock buffers for specific inputs
module my_design (o, i, clk_in) ;
output o;
input i;
input clk_in /* synthesis syn_noclockbuf=1 */;
Solution 2:
Use the Synplify constraints file (SDC) for passing vendor-specific attributes.
The syntax for specifing a normal buffer rather than a clock buffer resource for
the clock signal.
define_attribute {input_clock_port} syn_noclockbuf 1
A global specification can be used to specify use of normal buffers rather than
clock buffers for all clock signals.
define_global_attribute syn_noclockbuf 1
Solution 3:
VHDL
----------
To turn off automatic clock buffers for entire architectures
library IEEE, synplify;
use IEEE.std_logic_1164.all;
use synplify.attributes.all;
entity my_design is
port (o : out std_logic;
i, clk_in : in std_logic);
end entity;
architecture Xilinx of my_design is
attribute syn_noclockbuf of Xilinx : architecture is true;
To turn off automatic clock buffers for specific inputs
library IEEE, synplify;
use IEEE.std_logic_1164.all;
use synplify.attributes.all;
entity my_design is
port (o : out std_logic;
i, clk_in : in std_logic);
atttribute syn_noclockbuf of clk_in : signal is true;
end entity;
End of Record #4084 - Last Modified: 02/19/99 16:47 |
