Answers Database
FPGA Configuration: State of Dout pin before configuration.
Record #4190
Problem Title:
FPGA Configuration: State of Dout pin before configuration.
Problem Description:
Urgency: Standard
General Description: Users can delay configuration by holding
the INIT pin low. This will cause the IO of the device to be
tristated with the exception of Dout.
Solution 1:
When the user holds PROG or INIT low before configuration, Dout
will be driving a '1'. The '1' will be driven until
configuration begins at which time the 40 bit header will be
passed or the device starts to pass on data in a daisy chain.
For more information on configuration, please see the data
book.
End of Record #4190 - Last Modified: 11/10/98 15:50 |
