Answers Database
2.1i/1.5 VIEWLOGIC: Viewsim direct gate level schematic simulation of Virtex designs is partially supported
Record #4318
Product Family: Software
Product Line: ViewLogic
Product Part: Workview Office
Product Version: 7.5
Problem Title:
2.1i/1.5 VIEWLOGIC: Viewsim direct gate level schematic simulation of Virtex designs is
partially supported
Problem Description:
Urgency: standard
General Description:
Viewlogic Viewsim direct gate level schematic simulation of Virtex designs
is only partially supported. Some components are not simulatable in the Virtex
Viewlogic library.
Please refer to (Xilinx Answer #5968) for a list of these components.
Solution 1:
Customers trying to simulate a Viewlogic schematic design containing
unsimulatable library components can still simulate their Virtex designs using
VHDL or Verilog instead.
The following steps may apply to any HDL simulation tool.
Verilog Flow:
- edifneto -l xilinx <design_name>
- ngdbuild -p v000 <design_name>
- ngd2ver <design_name>.ngd
VHDL Flow:
- edifneto -l xilinx <design_name>
- ngdbuild -p v000 <design_name>
- ngd2vhdl <design_name>.ngd
End of Record #4318 - Last Modified: 01/17/00 11:39 | 
