Answers Database
Exemplar: How to initialize RAM or ROM in VHDL code
Record #4328
Product Family: Software
Product Line: Exemplar
Product Part: Exemplar
Problem Title:
Exemplar: How to initialize RAM or ROM in VHDL code
Problem Description:
Urgency: Standard
General Description:
I have either inferred or instantiated RAM or ROM in my HDL code. How can
I initialize the RAM/ROM contents to a known value so after programming the
part, the memory element will contain a predetermined value?
Solution 1:
An INIT attribute can be passed by the Exemplar Leonardo or Galileo synthesis
tool by putting an INIT string in the HDL code and attaching the attribute
to the instance name. Code similiar to the following can be attached to an
instance name such as myram. An example of an instantiate 16x1 RAM using
the INIT string follows:
-- Ram Initialization Example
library IEEE;
use IEEE.std_logic_1164.all;
entity init_ram is
port ( D, A3, A2, A1, A0, WE : in std_logic;
O : out std_logic);
end init_ram;
architecture behav of init_ram is
component ram16x1
port ( D, A3, A2, A1, A0, WE : in std_logic;
O : out std_logic);
end component;
attribute init: string;
attribute init of myram: label is "FF00";
begin
myram: ram16x1 port map (D => D,
A3 => A3,
A2 => A2,
A1 => A1,
A0 => A0,
WE => WE,
O => O);
end behav;
Note that after processing the design through the Xilinx tools that when
verifying the RAM/ROM contents in EPIC the INIT value may appear different
than what was originally given. The is possible since PAR is given the
availability to move the address lines for better routability, and because
of this the INIT value will change accordingly.
End of Record #4328 - Last Modified: 07/27/98 07:57 |
