Answers Database


2.1i, 1.5, 1.4 COREGEN: How the PDA FIR Filter module calculates its full precision output width.


Record #4427

Product Family: Software

Product Line: Coregen

Product Part: Coregen

Product Version: 2.1i

Problem Title:

2.1i, 1.5, 1.4 COREGEN:	How the PDA FIR Filter module calculates its full precision output
width.



Problem Description:
Urgency : Standard

General Description:
The way the PDA FIR Filter module calculates full precision
output width may not be what the user expects.


Solution 1:

Maximum output width for the PDA FIR filter
is the number of bits required to rerpresent the largest
magnitude result that may appear at the filter output.

The process used to determine the filter's output port bit-width
is as follows:

   Largest Coefficient Magnitude (given the coefficient bit-width
   provided by the user) =

     2 ^ (Coefficient Bit Width - 1)

   Largest Sample Magnitude (given the data bit-width provided by
   the user) =

     2 ^ (Data Bit Width - 1) - 1 for signed data,
     2 ^ (Data Bit Width) -1 for unsigned data

   Largest Filter Output Magnitude (given the number of taps provided
   by the user) =

       (Largest Sample Magnitude) x (Largest Coefficient Magnitude) x
       (Number Of Taps)

Number Of Bits Required At Output Port =

    Log 2 ( Largest Filter Output Magnitude) + 2, rounded
            down to the nearest whole number

Given that not all coefficients will be as large as the Largest
Coefficient Value calculated above, the filter's RSLT output
port may, at times, be wider than necessary. Given a spe-
cific set of coefficients, the ideal output port bit-width may
be found manually by substituting the sum of the magni-
tudes of the coefficients for the product of the Largest
Coefficient Magnitude and the Number Of Taps.

That is,

   Largest Sample Magnitude (Given the data bit-width provided by
   the user) =

    2 ^ (Data Bit Width - 1)  - 1	   for signed data,
    2 ^ (Data Bit Width) - 1		    for unsigned data

   Largest Filter Output Magnitude (Given the coefficients provided
   by the user) =

      (Largest Sample Magnitude) x ( |C 0 | + |C 1 | + |C 2 | + ... + |C n | )

   Number Of Bits Required At Output Port =

     Log 2 ( Largest Filter Output Magnitude) + 2 , rounded-down
      to the previous whole number

The difference between the conservative bit-width calculated
by the Core Generator and the ideal bit-width calculated manually
represents the number of unnecessary MSBs that are included in
the filter?s output port. These bits may safely be dropped from the
filter?s output, and a small amount of logic trimming may occur as a
result.

As an example, take a symmetric 6-tap filter, signed input data, and
coefficients 1,-3,12,12,-3 and 1. The center coefficients require 5
bits to express, but the other coefficients require only 2 and 4 bits.
Assuming 6-bit sample data, the Core Generator
conservatively calculates that this filter requires a 12-bit
RSLT port. Given the specific coefficients, however, only 11
bits are actually necessary. As a result, for this particular application,
the MSB of the filter?s output may be discarded.


NORMALIZING COEFFICIENTS

Some users may normalize their coefficients to reduce the
amount of logic required to implement their filter. Doing
this guarantees that the filter will never overflow. In
this case, if full precision in the output is maintained,
this means that the overflow bits from each summation will all
end up as sign extension bits.

Users who normalize their coefficients may assume that the PDA
FIR module does an analysis and recognizes that the overflow
bits are unnecessary, but in actuality, the module does NOT
do such an analysis.

If the output grows by 3 bits for a given PDA FIR filter whose
coefficients have been normalized, this means that the 3 MSB's
of their result will always be sign extension bits.
If the result is positive, this means that the 3 MSB's of the
result will be 0's; if the result is negative, all 3 MSB's
will be 1's.

Now if the user selects an output width "W" which is LESS
than the calculated full precision output width for the
filter, only the "W" MSB's will be selected, and these will
always include the sign bits.




End of Record #4427 - Last Modified: 01/19/00 15:46

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!