Answers Database
Exemplar: How to Preset or initialize a flop to a '1', on powerup only, FPGA's
Record #4488
Product Family: Software
Product Line: Exemplar
Product Part: Exemplar
Problem Title:
Exemplar: How to Preset or initialize a flop to a '1', on powerup only, FPGA's
Problem Description:
Urgency: Standard
General Description:
Writing VHDL code, and using Exemplar for synthesis how can I have a flop
initialize to a '1' on powerup only? I do not need any user signals to
set the flop during operation. I am targeting an FPGA.
Solution 1:
If no user set is needed during operation and only a set '1' is needed
upon powerup you can describe a preset flop in the VHDL code, then
instantiate the ROCBUF that will connect to the set signal. The Xilinx
tools will automatically remove the ROCBUF during implmentation.
The following is an exaample of VHDL code to do the above:
-- Preset flop example
--
library IEEE;
use IEEE.std_logic_1164.all;
entity set_flop is
port (CLK, DATA, PRESET: in STD_LOGIC;
Q: out STD_LOGIC);
end set_flop;
architecture BEHAV of set_flop is
component ROCBUF
port (I : in STD_LOGIC;
O : out STD_LOGIC);
end component;
signal PRESET_int: STD_LOGIC;
begin
U1: ROCBUF port map (I => PRESET, O => PRESET_int);
S_FLOP: process (CLK, PRESET_int, DATA)
begin
if (PRESET_int='1') then
Q <= '1';
elsif (CLK'event and CLK='1') then
Q <= DATA;
end if;
end process;
end BEHAV;
End of Record #4488 - Last Modified: 08/26/98 15:15 |
