Answers Database
Exemplar:Tips on how to use blackbox EDIF and XNF netlists in HDL. (Coregen)
Record #4512
Product Family: Software
Product Line: Exemplar
Product Part: Exemplar
Problem Title:
Exemplar:Tips on how to use blackbox EDIF and XNF netlists in HDL. (Coregen)
Problem Description:
Urgency: Standard
General Description:
Using Exemplar for synthesis I want to instantiate an EDIF or XNF netlist
into my HDL code. The netlist is Standard Xilinx EDIF/XNF. The netlist may
have come from Coregen 1.4 (XNF), or Corgen 1.5 (EDIF).
Solution 1:
EDIF macro Flow
---------------
Assuming you already have a valid EDIF netlist for the macro you
want to instantiate into your HDL code.
1) Perform a blackbox instantiation of the EDIF netlist.
2) Proceed to the 'Leonardo Flow' or 'Galileo Flow' below.
Using Coregen 1.5
------------------
Coregen 1.5 will write out EDIF netlists for the particular module
you have created. By defulat Exemplar will only write the EDIF
netlist using parenthseis, so the Coregen EDIF netlist must match.
1) After starting up Coregen, select the Netlist Bus Format to be
parenthesis B().
2) Go through and make the appropriate selections and create the
module.
3) Proceed to the 'Leonardo Flow' or 'Galileo Flow' below.
Note: You may have to deselect the HDL instantiation template in
order to change the 'Netlist Bus Format', also called the bus
delimiter type, to parenthesis "()". If the HDL instantiation
template is needed you may have to run through Coregen twice
fora given module.
Leonardo Flow
-------------
Process the design as you normally would, except when going to
'Write' the EDIF netlist from Leonardo you must turn off writing of
bus arrays by doing one of the following:
1. In the Write dialog box (Menu: IO -> Write, or Flow Guide: Write),
click the Advanced button. In the Set Write Variables dialog box,
UNSELECT the following option:
Allow writing arrays (busses) in EDIF output
Click Set, then proceed with the EDIF Write as normal.
2. If you are processing the design from the Leonardo command line
or from a script file, add the following set command before your
write command:
set edif_write_arrays FALSE
Galileo Flow
------------
Process the design as you normally would, except that the bus
arrays must not be written in expanded form. There is no checkbox
that sets or unsets this option in the Galileo GUI. The change
can be made via a 'Special Option' in the GUI, or in
a command file:
1. In the Galileo GUI click on the Synthesis Options icon. In the
Synthesis Options windows add the following to the
'Special Options' field:
-nobus
2. Synthesize the design in Galileo as normal.
Using a Command File:
--------------------
1. If you do not already have a command file, create one in a text
editor. Add the following line to your command file:
-nobus
2. Set this newly created file as your command file. From the main
Galileo window, Choose Options -> Control Files from the menu bar,
or in the RUNTIME OPTIONS panel, click Control Files. In the
Logic Explorer Control Files dialog box, set the Command Files
field to the filename of the command file from Step 1,
then click OK.
3. Synthesize the design in Galileo as normal.
Solution 2:
XNF macro Flow
--------------
Assuming you have a valid XNF netlist for the macro you want to
instantiate in your HDL code.
1) Instantiate the XNF netlist as a blackbox in your HDL code.
2) Proceed to the 'Leonardo Flow and Galileo Flow' below.
Using Coregen 1.4
-----------------
Coregen 1.5 is the supported product to use with Exemplar. Please
upgrade to Coregen 1.5 if you are using Coregen 1.4.x or older.
Using Coregen 1.4 created XNF netlist for the module you create. The
XNF Spec will use bus delimeters of angle brackets '<>'.
1) Make the appropriate choices to create the macro. No special
options are needed.
2) Proceed to the 'Leonardo Flow and Galileo Flow' below.
Leonardo Flow and Galileo Flow
------------------------------
XNF netlist from Exemplar
-------------------------
This flow is straight-forward. Coregen generates an XNF netlist
with angle bracket bus delimiters, as does Exemplar. Nothing
additional needs to be done. With Coregen v1.4, this is the
simplest flow.
EDIF netlist from Exemplar
--------------------------
By default when writing out EDIF from Exemplar the bus delimeters
used will be parenthesis (). XNF spec is for bus delimeters to be
angle brackets <>, so going through the Xilinx core tools will
produce pin mismatch errors.
In order to resolve the pin mismatches between the different
bus delimiters, the Coregen XNF must be modified. Using a
text editor, replace all the occurences of angle brackets with
parentheses.
Additionally, bus arraying must be disabled as described by the
'Leonardo Flow' and 'Galileo Flow' in the 'EDIF macro Flow' sections.
End of Record #4512 - Last Modified: 08/30/98 15:04 |
