Answers Database
V1.5, V1.4 COREGEN: Only the 24 LSBs of a cascade mode SDA FIR output are defined in a Verilog behavioral simulation
Record #4543
Product Family: Software
Product Line: LogiCore
Product Part: Coregen IP Modules
Problem Title:
V1.5, V1.4 COREGEN: Only the 24 LSBs of a cascade mode SDA FIR output are defined in a
Verilog behavioral simulation
Problem Description:
Urgency: hot
General Description:
In a Verilog behavioral simulation of the Coregen SDA FIR
filter in cascade mode, only the lower 24 bits of a 32-bit
output are defined. All upper bits are stuck at X.
Solution 1:
The problem is that the "full_result_width" parameter is
declared with a value of 24, which effectively limits the
precision with which the output can be reported.
The fix is to extend the bus width parameter value to 100 bits
in the SDA FIR Verilog behavioral model:
The line that needs to be modified is preceded by this
comment:
//Start of constant declarations - do not overload
The parameter, "full_result_width", on line 77 needs to be
changed from 24 to 100:
parameter full_result_width = 100;
This problem is only seen in the Verilog version of the
behavioral model and has been fixed in the 1.5.2
CORE Generator patch.
End of Record #4543 - Last Modified: 08/17/99 09:57 |
