Xilinx Answer #4610 : COREGEN: How to calculate the clock/pipeline latency of the COREGEN PDA FIR filter

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COREGEN: How to calculate the clock/pipeline latency of the COREGEN PDA FIR filter

Record #4610
Product Family: Software

Product Line: LogiCore

Product Part: Coregen IP Modules

Problem Title:
COREGEN: How to calculate the clock/pipeline latency of the COREGEN PDA FIR filter

Problem Description:
Urgency: standard

General Description:
How to calculate the pipeline/clock latency of the CORE
Generator PDA FIR filter.

Solution 1:

For Symmetric PDA Filters,
--------------------------
the pipeline latency is:

       2 + (1*is_the_number_of_taps >10)
      + log_to_the_base_2_and_rounded_up (number_of_input_data_bits +1)
      -1;

Example:
--------

For a PDA FIR Filter with the following characteristics:

- 16-bit data & coefficients,
- 4 Taps,
- symmetric,
- serial or parallel implementation.

latency = 2 + (1*0) + log_to_the_base_2_and_rounded_up(16+1) -1 = 2 + 0 + 5 -1 = 6

For non-Symmetric PDAs,
----------------------

latency = 1 + (1*is_the_number_of_taps >5)
             +
log_to_the_base_2_and_rounded_up(number_of_input_data_bits)
             -1;

End of Record #4610 - Last Modified: 10/23/98 16:21

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