Answers Database
BITGEN M1.5: SpartanXL Power Down Pin Configured Improperly.
Record #4810
Product Family: Software
Product Line: FPGA Implementation
Product Part: bitgen
Product Version: 1.5
Problem Title:
BITGEN M1.5: SpartanXL Power Down Pin Configured Improperly.
Problem Description:
Urgency: Standard
General Description:
The Power Down pin on the SpartanXL device will tri-state all
IO's, assert GSR and stop the clock. This pin is active low,
thus driving the pin low will cause the above to happen.
*** The Following is fixed in M1.5i ***
The default option for M1.5 BITGEN is for the internal pullup
to be active for the Power Down pin. However, the opposite
occurs when configuring the device. Thus, possibly causing the
device to not configure or function properly.
Solution 1:
To workaround this problem, simply choose the opposite
functionality.
To change this option, in the 1.5 Design Manager -> go to
Implement -> Options -> Edit Template (for Configuration).
On this tab, there is a section titled 'Configuration Pins'
To have the pin 'Pulled High' select 'Float'
To have the pin 'Floating' select 'Pullup'
Solution 2:
If using command line to create the bitstream (BITGEN):
To have the pin 'Pulled High' use the BITGEN option:
'-g PowerDown Pullnone'
To have the pin 'Floating' use the BITGEN option:
'-g PowerDown Pullup'
End of Record #4810 - Last Modified: 12/11/98 14:44 |
