Answers Database
FPGA Express: modules for black boxes (LogiBLOX, CoreGen) must be declared in Verilog designs; clock pins missing
Record #5008
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 2.1.3
Problem Title:
FPGA Express: modules for black boxes (LogiBLOX, CoreGen) must be declared in Verilog
designs; clock pins missing
Problem Description:
Urgency: Standard
General Description:
When black boxes are instantiated in a Verilog design (for LogiBLOX and CoreGen,
for example), a module declaration is required to let Express know the port
directions and sizes. If this module declaration is missing, the clock pin may
be left out of the instantiation.
Solution 1:
For LogiBLOX and CoreGen designs, use the .VEI file to obtain the module
declaration. Only the portion of this file from the "module" to "endmodule"
keywords is necessary. For other black boxes, this declaration must be written
by the user.
This declaration can exist in any of the Verilog files added to the project, or
within its own unique .V file. It should look like the following:
module count (CLK_EN, CLOCK, ASYNC_CTRL, Q_OUT, TERM_CNT);
input CLK_EN;
input CLOCK;
input ASYNC_CTRL;
output [7:0] Q_OUT;
output TERM_CNT;
endmodule
End of Record #5008 - Last Modified: 11/09/98 15:12 |
