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VERILOG-XL: Timing violation: $recovery(posedge CLKB: 800, posedge CLKA: 800, 1.0: 10)Record #5178
Product Family: Software // add near the top of the file (among other declarations) reg addr_equal; // at the end of the file add and modify the code to: always @(addra_int or addrb_int) begin if (addra_int == addrb_int) addr_equal=1; else addr_equal=0; end specify (CLKA => DOA) = (1, 1); (CLKB => DOB) = (1, 1); $recovery (posedge CLKB, posedge CLKA &&& addr_equal, 1, recovery_b); $recovery (posedge CLKA, posedge CLKB &&& addr_equal, 1, recovery_a); endspecify The 'always' statement just sets the variable 'addr_equal' to 1 if the addresses happen to be equal. The recovery statements are made conditional to this event by adding the '&&&' operator. The $recovery is a Verilog system task which limits a change in an asynchronous control signal and the next clock pulse. Please see (Xilinx Solution 1655) for details about the $recovery system task. End of Record #5178 - Last Modified: 07/14/99 13:33 |
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