Answers Database
VCS: Running simulation
Record #5263
Product Family: Software
Product Line: ViewLogic
Product Part: VCS
Problem Title:
VCS: Running simulation
Problem Description:
Urgency: Standard
General Description:
How to run simulation with VCS?
There are two methods to run simulation with VCS:
- Using library source files with compile-time options (similar to Verilog-XL)
- Using shared pre-compiled libraries
Please see (Xilinx Solution 6330) on how to compile the Alliance 2.1i
libraries for VCS.
Solution 1:
Using library source files with compile-time options (similar to Verilog-XL):
Depending on the makeup of the design (LogiBlox, Xilinx instantiated
primitives, or Coregen components), for RTL simulation, specify the
following at the command-line:
vcs -y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/simprims \
-y <path_coregen>/XilinxCoreLib +libext+.v $XILINX/verilog/src/glbl.v \
-Mupdate -R <testfixture>.v <design>.v
The $XILINX/verilog/src/unisims area contains the Unified components
for RTL simulation. The $XILINX/verilog/src/simprims area contains generic
simulation primitives for LogiBlox. The XilinxCoreLib area contains the Coregen
components for RTL simulation. Please see (Xilinx Solution 7859) for instructions
on extracting this library.
The -Mupdate option enables incremental compilation. The -R option
automatically simulates the executable after compilation .
For timing simulation or post-Ngd2ver, the Simprims-based libraries are used.
Specify the following at the command-line:
vcs +compsdf -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v \
+libext+.v -Mupdate -R <testfixture>.v time_sim.v
Please see (Xilinx Solution 6349) on how to back-annotate the SDF file for timing
simulation.
Solution 2:
Using shared pre-compiled libraries:
Simulation Libraries have to be compield to <compiled_lib_dir> before
using VCS. See (Xilinx Solution 6330) for instruction on how to compile
the Xilinx Verilog libraries for VCS.
Depending on the makeup of the design (LogiBlox, Xilinx instantiated
primitives, or Coregen components), for RTL simulation, specify the
following at the command-line:
vcs -Mupdate -Mlib=<compiled_dir>/unisims_ver -y $XILINX/verilog/src/unisims \
-Mlib=<compiled_dir>/simprims_ver -y $XILINX/verilog/src/simprims \
-Mlib=<compiled_dir>/xilinxcorelib_ver -y <path_coregen>/XilinxCoreLib \
+libext+.v $XILINX/verilog/src/glbl.v -R <testfixture>.v <design>.v
The unisims_ver area contains the Unified components for RTL simulation.
The simprims_ver area contains generic simulation primitives for LogiBlox. The
XilinxCoreLib area contains the Coregen components for RTL simulation. Please
see (Xilinx Solution 7859) for instructions on extracting this library.
The -Mupdate option enables incremental compilation. The -R option
automatically simulates the executable after compilation. Finally, the
-Mlib=<compiled_lib_dir> option provides VCS with a central place to look for
the descriptor information before it compiles a module and a central place to
get the object files when it links together the executable.
For timing simulation or post-Ngd2ver, the Simprims-based libraries are used.
Specify the following at the command-line:
vcs +compsdf -Mupdate -Mlib=<compiled_lib_dir>/simprims_ver \
-y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v +libext+.v \
-R <testfixture>.v time_sim.v
Please see (Xilinx Solution 6349) on how to back-annotate the SDF file for timing
simulation.
End of Record #5263 - Last Modified: 11/12/99 17:21 |
