Answers Database
1.5i 4KX* MAP - FATAL_ERROR:xvkma:xvkmapper.c:1691:1.113 - Cannot satisfy LOC/RLOC constraint on comp H14/H57/I610/$1I106/$1I64 Process will terminate. Cannot satisfy LOC/RLOC constraint on comp H14/H57/I610/$1I106/$1I64 Process will terminate.
Record #5663
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.5is1
Problem Title:
1.5i 4KX* MAP - FATAL_ERROR:xvkma:xvkmapper.c:1691:1.113 - Cannot satisfy LOC/RLOC
constraint on comp H14/H57/I610/$1I106/$1I64 Process will terminate. Cannot satisfy LOC/RLOC constraint
on
comp H14/H57/I610/$1I106/$1I64 Process will terminate.
Problem Description:
Urgency: standard
General Description:
FATAL_ERROR:xvkma:xvkmapper.c:1691:1.113 - Cannot satisfy LOC/RLOC constraint
on comp H14/H57/I610/$1I106/$1I64 Process will terminate. Please call Xilinx
support.
Solution 1:
This may be the result of a carrychain loop. For example: the Cout of a counter feeding the Cin of
the same counter.
For now, the user must manually break the carrychain loop. put a BUF between the final Cout and the
first Cin. Then put keep attributes on the nets connected to the the BUF.
This problem is fixed in version 2.1 due out in June, 1999.
End of Record #5663 - Last Modified: 05/18/99 13:41 |
