Answers Database
Design Manager 2.1i: Non-timing driven implementation of Virtex/VirtexE/Spartan2 can result in lower design performance
Record #5684
Product Family: Software
Product Line: M1 Graphical/General
Product Part: Design Manager
Product Version: 2.1i
Problem Title:
Design Manager 2.1i: Non-timing driven implementation of Virtex/VirtexE/Spartan2 can result
in lower design performance
Problem Description:
Urgency: HOT
General Description:
To improve runtime for timing driven implementation, the PAR command line
defaults for the Virtex, VirtexE, and Spartan2 families in M2.1i have
changed to NOT run Cost Based and Delay Based Clean-up passes. Because of
this change, you may notice lower design performance results from PAR when
targeting these families. This will occur on designs that are run in M2.1i with
no timing constraints applied (non-timing driven).
Solution 1:
To get a more "realistic" estimate of how your design will perform without any
timing constraints applied, please follow this recommendation:
1. Implement your design until PAR has completed.
2. Open up the Flow Engine on your (Routed,OK) revision.
3. Under Setup-> FPGA Re-entrant Route, specify the number of
clean-up passes to be run.
4. Click OK
5. In the Flow Engine, select Flow->Step Back
6. Select Flow->Run
Check the Reports Browser (P&R Report/Post Layout Timing Report) for improved
performance results.
End of Record #5684 - Last Modified: 06/22/99 19:54 |
