Answers Database
1.5i Map - WARNING:xvkdr:3 - blockcheck: Dangling CYINIT input. CYINIT of comp
Record #5930
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.5i
Problem Title:
1.5i Map - WARNING:xvkdr:3 - blockcheck: Dangling CYINIT input. CYINIT of comp
Problem Description:
Urgency: Standard
This is caused by a dangling CIN net with no driver. This net should
have been trimmed by Map but was not. The resulting DRC issue is an
error in bitgen.
ERROR:xvkdr:3 - blockcheck: Dangling CYINIT input. CYINIT of comp
io_int/cmd_fifo_reg_1[6] is configured to use pin CIN, but pin CIN is not
connected.
Solution 1:
This problem can be worked around by deleting the stub in the routed
ncd in EPIC and then running bitgen.
This problem is corrected in the 2.1i release due to ship in June.
Solution 2:
Turn off the DRC when running bitgen. Use the -d option in the utilities->customize->
template manager.
End of Record #5930 - Last Modified: 05/24/99 10:28 |
