Answers Database
2.1i COREGEN: Required order of analysis/compilation for CORE Generator VHDL and Verilog behavioral model libraries
Record #6250
Product Family: Software
Product Line: Coregen
Product Part: Coregen
Product Version: 2.1i
Problem Title:
2.1i COREGEN: Required order of analysis/compilation for CORE Generator VHDL and Verilog
behavioral model libraries
Problem Description:
Urgency: hot
General Description:
There is a definite hierarchical relationship between the VHDL behavioral models
delivered by Coregen which must be considered in order for them to be compiled
without error in preparation prior to simulation. For VHDL the hierarchy must be compiled from
the bottom up--i.e., "primitive" models must be compiled or analyzed before the "macro"
models in which they are instantiated.
For Verilog, the compilation order is not critical, but using the recommended compile order
will minimize the number of warnings issued during the compile process.
Solution 1:
VHDL:
The required order for the models shipped in the C_IP2 release is:
prims_constants*.vhd
prims_comps*.vhd
prims_utils*.vhd
prims_sim_arch*.vhd
ul_utils.vhd
*pack.vhd
c_*comp.vhd
c_reg*.vhd
c_*.vhd
*.vhd
The last item in the list will cause some models to be recompiled, but
this is not a problem--no errors will be issued by ModelSIM about
recompiled models. The only requirement that needs to be met is
that any lower level models need to be compiled before the higher
level ones.
The required order shown above may change slightly with each IP update
that Xilinx ships, but updated information on compile order requirements
will be included with each such update as well as this solution record.
Solution 2:
The required order for the VHDL models shipped in the C_IP3 release is:
prims_constants*.vhd
prims_comps*.vhd
prims_utils*.vhd
prims_sim_arch*.vhd
ul_utils.vhd
*pack.vhd
c_*comp.vhd
c_reg*.vhd
c_addsub_v1_0.vhd
c_mux_bus_v1_0.vhd
c_*.vhd
*.vhd
The recommended order for compiling the XilinxCoreLib Verilog libraries in C_IP3 is:
C_REG_FD_V1_0.v
C_ADDSUB*.v
*.v
Solution 3:
For the C_IP4 release, you must make sure that the UNISIM library is compiled first before
the XilinxCoreLib library.
The UNISIM library is located in $XILINX/vhdl/src. You will need to compile the following files:
unisim_VPKG.vhd
unisim_VCOMP.vhd
Sample commands for compiling the UNISIM library for ModelSIM are as follows:
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VPKG.vhd
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
vcom -87 -work unisim $XILINX/vhdl/src/unisims/unisim_VCFG4K.vhd
XILINXCORELIB Compilation
-------------------------------------------
When compiling the XilinxCoreLib library, the required order for the VHDL models shipped in the
C_IP4 release is (be sure to include the "*" symbol):
prims_constants*.vhd
prims_comps*.vhd
prims_utils*.vhd
prims_sim_arch*.vhd
ul_utils.vhd
*pack.vhd
c_*comp.vhd
c_reg*.vhd
c_addsub*.vhd
c_mux_bus*..vhd
c_*.vhd
vfft_utils.vhd
*.vhd
The recommended order for compiling the XilinxCoreLib Verilog libraries in C_IP4 is:
C_REG_FD_V1_0.v
C_ADDSUB*.v
*.v
End of Record #6250 - Last Modified: 01/20/00 13:47 |
