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V2.1i COREGEN, VERILOG, VHDL: New HDL behavioral simulation flow does not generate .VHD and .V models for simulation


Record #6556

Product Family: Software

Product Line: Coregen

Product Part: Coregen

Product Version: 2.1

Problem Title:
V2.1i COREGEN, VERILOG, VHDL: New HDL behavioral simulation flow does not generate .VHD and .V models for simulation



Problem Description:
Urgency: standard

General Description:
In the new 2.1i release, the CORE Generator does not directly generate
.VHD and .V models for behavioral simulation. (.VEO and .VHO templates
are generated instead).



Solution 1:

1. The 2.1i CORE Generator does not generate a .VHD or .V
     file for each core in the 2.1i release.
     Instead, it creates a .VHO (for VHDL) or .VEO (for Verilog) template file
     containing the code snippets required to integrate the core into a
     higher level design block's behavioral simulation netlist.

2. Before any behavioral simulation of a core can be done,
     you must :

  - run the get_models utility to extract the models into a separate source
    library,

  - analyze the library, if required by your simulator, to a library named "xilinxcorelib".
    (VHDL and compiled Verilog simulators)

  - set your simulator to point to the extracted (and analyzed) library

Please refer to the Design Flows chapter of the CORE Generator User Guide
(available from within the CORE Generator under Help->Online Documentation)
for more details. The latest version is accessible at:
http://support.xilinx.com/support/techsup/journals/coregen/2.1i/ug2_1a.pdf
The details are documented in the HDL Design Flows section of the last chapter.




End of Record #6556 - Last Modified: 10/13/99 10:42

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