Answers Database JTAG BSDL - Does Xilinx provide configured BSDL files for post configured parts? Record #6664 Problem Title: JTAG BSDL - Does Xilinx provide configured BSDL files for post configured parts? Problem Description: Urgency: Standard General Description: A configured BSDL file represents a Xilinx device containing the users design information. How does the user obtain a BSDL file based on the design loaded in the part? Solution 1: Most users do not need the post configuration BSDL representation of their part. Unless you are doing configured JTAG testing of our device, the preconfigured BSDL files without any modifications is choice. All Xilinx BSDL files can be found under the BSDL link at: http://support.xilinx.com/support/software.htm Solution 2: The released BSDL files match JTAG behavior prior to completion of configuration. The BSDL file without any modifications has all i/o's defined as tristate capabile bidirectional pins. After configuration, most pins are usually configured as an input or an output, not tristate capabile bidirectional. If the user desires a BSDL file that matches the behavior of the chip after their design has been loaded, some alterations are necessary. This document describes the steps necessary to create such a BSDL file for Virtex. Any other families may require more or less steps to generate the file. Instructions: To create a post-configuration BSDL file (quoted exactly from actual BSDL files): -- 1. Enable USER instructions as appropriate (see below). -- 2. Set disable result of all pads as configured. -- 3. Set safe state of boundary cells as necessary. -- 4. Rename entity if necessary to avoid name collisions. -- 5. Modify USERCODE value in USERCODE_REGISTER declaration. Instructions (with explanation) 1. Enable USER instructions as appropriate. If you do not use the user instructions, no modifications are needed. If you use either USER1 or USER2, include appropriate entries in the REGISTER_ACCESS description. For more information, consult Supplement (B) to IEEE Std 1149.1 2. Set disable result of all pads as configured. The disable result is the value of the signal when it is disabled. It is specified in the BOUNDARY_REGISTER section of the BSDL file. If pullup = NO and pulldown = NO, then the disable result value is Z If pullup = YES and pulldown = NO, then the disable result value is PULL1 If pullup = NO and pulldown = YES, then the disable result value is PULL0 Unused pads are PULL0 Following are three BSDL code examples of how to modify the BOUNDARY_REGISTER section. For this example, code has been used from Revision: 1.2 of xcv100_pq240.bsd This is what the code looks like that is not touched: attribute BOUNDARY_REGISTER of XCV100_PQ240 : entity is -- cellnum (type, port, function, safe[, ccell, disval, disrslt]) " 0 (BC_1, *, controlr, 1)," & " 1 (BC_1, PAD60, output3, X, 0, 1, PULL0)," & " 2 (BC_1, PAD60, input, X)," & " 3 (BC_1, *, controlr, 1)," & " 4 (BC_1, PAD59, output3, X, 3, 1, PULL0)," & " 5 (BC_1, PAD59, input, X)," & " 6 (BC_1, *, internal, X)," & " 7 (BC_1, *, internal, X)," & " 8 (BC_1, *, internal, X)," & " 9 (BC_1, *, controlr, 1)," & " 10 (BC_1, PAD57, output3, X, 9, 1, PULL0)," & " 11 (BC_1, PAD57, input, X)," & " 12 (BC_1, *, controlr, 1)," & If pin 57 has been configured as a bidirectional pin, no code modifications are required: -- UNCONFIGURED OR BIDIRECTIONAL PIN: " 9 (BC_1, *, controlr, 1)," & " 10 (BC_1, PAD57, output3, X, 9, 1, PULL0)," & " 11 (BC_1, PAD57, input, X)," & If pin 57 is configured an input, then you should modify it as such: -- PIN CONFIGURED AS AN INPUT " 9 (BC_1, *, internal, 1)," & " 10 (BC_1, *, internal, X)," & " 11 (BC_1, PAD57, input, X)," & If pin 57 is configured an output, then you should modify it as such: -- PIN CONFIGURED AS AN OUPUT " 9 (BC_1, *, internal, 1)," &       " 10 (BC_1, PAD57, output2, X)," &       " 11 (BC_0, PAD57, observe_only, X)," & repeat these modifications for every configured pin in your design. 3. Set safe state of boundary cells as necessary. The safe bit supplies a value that should be loaded when board-level test generation software might otherwise choose a value randomly (it is not forcing). The safe bit has several example uses: 1. The value in a control cell that turns off its associated drivers 2. The value that an output should have during INTEST that       minimizes driver current 3. A preferred value to present to on-chip logic at a component       input during EXTEST The control cells (corresponding to the tri-state of the pad) that already have the proper value, don't need to change them. The output and input values are design dependent. Knowledge of the user's application is necessary to set these (can't be automatically done based solely on the .ncd). 4. Rename entity if necessary to avoid name collisions. If the entity name used in the BSDL file causes a collision with other BSDL or VHDL files, then you must rename the entity. 5. Modify USERCODE value in USERCODE_REGISTER declaration. Fill in USERCODE value supplied during bitgen if using this function. End of Record #6664 - Last Modified: 01/04/00 19:58

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