Answers Database
VERILOG-XL: Running simulation
Record #6701
Product Family: Software
Product Line: Cadence
Product Part: Verilog-XL
Product Version: 2.5
Problem Title:
VERILOG-XL: Running simulation
Problem Description:
Urgency: Standard
General Description:
How to run simulation with Verilog-XL?
Solution 1:
Depending on the makeup of the design (LogiBlox, Xilinx instantiated
primitives, or Coregen components), for RTL simulation, specify the
following at the command-line:
verilog -y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/simprims \
-y <path_coregen>/XilinxCoreLib +libext+.v $XILINX/verilog/src/glbl.v \
<testfixture>.v <design>.v
The $XILINX/verilog/src/unisims area contains the Unified components
for RTL simulation. The $XILINX/verilog/src/simprims area contains
generic simulation primitives for LogiBlox. The XilinxCoreLib area contains
the Coregen components for RTL simulation. Please see
(Xilinx Solution 7859) for instructions on extracting this library.
For timing simulation or post-Ngd2ver, the Simprims-based libraries are used.
Specify the following at the command-line:
verilog -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v \
+libext+.v <testfixture>.v <design>.v
Please see (Xilinx Solution 3167) on how to specify the Xilinx
Simprims libraries using the -ul switch with ngd2ver instead of using
the -y switch in Verilog-XL.
End of Record #6701 - Last Modified: 12/16/99 13:17 |
