Answers Database
V2.1i COREGEN, VHDL: "**Error: Library logical name ARITHMETIC is not mapped to a host directory"
Record #6771
Product Family: Software
Product Line: Coregen
Product Part: Coregen
Product Version: 2.1
Problem Title:
V2.1i COREGEN, VHDL: "**Error: Library logical name ARITHMETIC is not mapped to a host
directory"
Problem Description:
Urgency: hot
General Description:
The following error message may be seen while analyzing the CORE Generator VHDL libraries
extracted using the get_models script:
**Error: vhdlan,1071 /home/magruder2/prod_apps/karlton/testing/cgentest/2.1/testarith/XilinxCoreLib/
prims_sim_arch.vhd(86):
Library logical name ARITHMETIC is not mapped to a host directory.
use arithmetic.std_logic_arith.all;
^
**Error: vhdlan,573 /home/magruder2/prod_apps/karlton/testing/cgentest/2.1/testarith/XilinxCoreLib/p
rims_sim_arch.vhd(87):
No selected element named STD_LOGIC_ARITH is defined for this prefix.
architecture behavioral of c_lut is
^
**Error: vhdlan,1084 /home/magruder2/prod_apps/karlton/testing/cgentest/2.1/testarith/XilinxCoreLib/
prims_sim_arch.vhd(103):
The intermediate file for entity C_LUT is not in the library bound to WORK.
configuration cfg_beh of c_lut is
^
**Error: vhdlan,1019 /home/magruder2/prod_apps/karlton/testing/cgentest/2.1/testarith/XilinxCoreLib/
prims_sim_arch.vhd(152):
The intermediate file for the entity-architecture pair C_LUT(BEHAVIORAL) is
not in the library bound to WORK.
The problem will be seen all VHDL simulators except for MTI v5.2e
The problem is that the prims_sim_arch.vhd VHDL file references a ModelSIM MTI-
specific library called "arithmetic".
Solution 1:
This problem has been fixed in the latest IP update, which is accessible from
http://www.xilinx.com/ipcenter/coregen/updates.htm#updatesCurrent
Solution 2:
If unable to download the indicated update, the model may be modified manually
as follows:
Two modifications must be made to the extracted model, prims_sim_arch.vhd to fix
this problem:
1. Comment out the references to the "arithmetic" library on lines 86 and 87 of
prims_sim_arch.vhd:
83 Library IEEE;
84 Use IEEE.std_logic_1164.all;
85 use IEEE.std_logic_arith.all;
86 -- library arithmetic;
87 -- use arithmetic.std_logic_arith.all;
2. Edit line 144 as follows:
ORIGINAL: addr := conv_integer('0' & addr_slv);
CHANGE TO: addr := conv_integer(unsigned('0' & addr_slv));
End of Record #6771 - Last Modified: 11/29/99 10:54 |
