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V2.1i COREGEN, SYNOPSYS VSS, LEAPFROG VHDL: " **Error "OTHERS is not legal in this context as it is not the only element association AND the choice is not locally static"
Record #6772
Product Family: Software
Product Line: Coregen
Product Part: Coregen
Product Version: 2.1i
Problem Title:
V2.1i COREGEN, SYNOPSYS VSS, LEAPFROG VHDL: " **Error "OTHERS is not legal in this context
as it is not the only element association AND the choice is not locally static"
Problem Description:
Urgency: hot
General Description:
The following errors are issued by VSS against the Virtex single and dual port block RAM
models (c_mem sp_v1_0.vhd and c_mem dp_v1_0 .vhd, respectively) when the VHDL
XilinxCoreLib libraries are analyzed:
**Error: vhdlan,739 /home/magruder2/prod_apps/karlton/testing/cgentest/2.1/testarith/XilinxCoreLib/c_mem_dp_block_v1_0.vhd(260):
OTHERS is not legal in this context as it is not the only element association
AND the choice is not locally static.
VARIABLE MULT10 : STD_LOGIC_VECTOR(size-1 DOWNTO 1) := (OTHERS=>'0');
^
**Error: vhdlan,1072 /home/magruder2/prod_apps/karlton/testing/cgentest/2.1/testarith/XilinxCoreLib/
c_mem_dp_block_v1_0.vhd(261):
Illegal redeclaration of MULT10.
"/home/magruder2/prod_apps/karlton/testing/cgentest/2.1/testarith/XilinxCoreLib/c_mem_dp_block_v1_0.vhd": errors: 2; warnings: 0.
VARIABLE MULT10 : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (0=>'1', OTHERS=>'0');
^
**Error: vhdlan,739 /home/magruder2/prod_apps/karlton/testing/cgentest/2.1/testarith/XilinxCoreLib/c_mem_sp_block_v1_0.vhd(174):
OTHERS is not legal in this context as it is not the only element association
AND the choice is not locally static.
Solution 1:
The problem appears to be with the initialization of the variable MULT10 on line 259
of c_mem_dp_block_v1_0.vhd and line 174 of c_mem_sp_block_v1_0.vhd.
Currently the declaration reads as:
VARIABLE MULT10 : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (0=>'1', OTHERS=>'0');
The problem appears to be the attempt to declare two different parts of the array at once.
If rewritten to initialize all of MULT10's location to '0' first, and bit 0 is initialized within the body
of the function, this problem goes away:
VARIABLE MULT10 : STD_LOGIC_VECTOR(size-1 DOWNTO 0) := (OTHERS=>'0');
VARIABLE MULT : STD_LOGIC_VECTOR(size-1 DOWNTO 0);
BEGIN
MULT10 (0) := '1';
FOR i IN arg1'REVERSE_RANGE LOOP
End of Record #6772 - Last Modified: 01/26/00 11:28 |
