Exemplar Logic Interface: Documentation

Design Flow

The Watch Design Exemplar Tutorial is a flow based tutorial taking the Verilog/VHDL Design files through Exemplar Leonardo Spectrum 1998.2e for synthesis. The tutorial includes presynthesis Functional Simulation, and a post place and route (PAR) Timing Simulation, both using the Model Technology ModelSim simulator.
Synthesis and Simulation Design Guide, 4/98 (1.3 MB)
Manual providing a general overview for designing into FPGAs using VHDL and Verilog including Verilog simulation techniques.

Xilinx: Backannotated Static Timing Analysis (30 KB)
Using Leonardo Spectrum to augment Xilinx's software timing analysis tools, by providing additional functionality such as graphical constraint setting, critical path identification and schematic correlation and cross highlighting.

Xilinx: Large Device Design Methodology (384 KB)
Virtex (Large Device) Design Methodology using LeonardoSpectrum 1999.1

Using Xilinx and Exemplar for Incremental Designing (ECO)
Guided place and route (PAR) can help you reduce runtimes when incremental changes are made to a design, such as for an Engineering Change Order (ECO). By making only small changes to a design along with optimizing only the changed block(s), you allow guided PAR to perform at its best, preserving timing and reducing PAR runtimes. To localize the design changes without affecting the remainder of your design, either a top-down preserving hierarchy or a bottom-up methodology must be used.

Xilinx: RAM Inference using Exemplar Logic's Leonardo (16 KB)
How to write code to infer Xilinx RAM components using Exemplar's LeonardoSpectrum.

Xilinx: RTL RAM Inference (14 KB)
How to write code to infer Xilinx RAM components using Exemplar's Leonardo.

Xilinx: Spartan 33MHz PCI Core (33 KB)
This applications note describes the synthesis flow using LeonardoSpectrum targeting the Verilog version of the Xilinx LogiCORE PC132 PCI core for the Spartan architecture. A user design "Ping" is included to demonstrate the use of the PC132 PCI core in an HDL design flow.

Xilinx: Virtex 66MHz PCI Core - Verilog (33 KB)
This applications note describes the synthesis flow using LeonardoSpectrum targeting the Xilinx LogiCORE PC132 PCI core for the Virtex architecture. A user design "Ping" is included to demonstrate the use of the PC132 PCI core in an HDL design flow.

Xilinx: Virtex 66MHz PCI Core - VHDL (33 KB)
This applications note describes the synthesis flow using LeonardoSpectrum targeting the Xilinx LogiCORE PC132 PCI core for the Virtex architecture. A user design "Ping" is included to demonstrate the use of the PC132 PCI core in an HDL design flow.