File Archive: app_xapp
Contents of /pub/applications/xapp
Application design files for XAPP Application Notes
See /apps/xapp.htm for more information.
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Filename Size File Description
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i2c_customer_pack.zip
503 Kb Uploaded: 01-04-2000
ZIP file containing VHDL source files, VHDL test
benches, and CoolRunner CPLD compilation and
fitter files for the I2C Controller Design
For All Platforms
io_lvds.tar.gz
46 Kb Uploaded: 02-11-2000
HDL files supporting the use of registers for
LVDS and LVPECL I/O. Includes Verilog, VHDL and
Edif versions, as well as Synopsys and Synplify
formats.
Solution #: xapp133
For All Unix
SW Release: All
io_lvds.zip
89 Kb Uploaded: 02-11-2000
HDL files supporting the use of registers for
LVDS and LVPECL I/O. Includes Verilog, VHDL and
Edif versions, as well as Synopsys and Synplify
formats.
Solution #: xapp133
For All Windows
SW Release: All
xap4001v.zip 149KB 60 MHz Counters, 8 to 24 bits long
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4002v.zip 273KB Loadable Up/Down Counters, 8 to 24 bits long
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4003v.zip 196KB Synchronous Presettable Up and Down Counters,
8, 12, and 16 bits long
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4004v.zip 350KB Loadable Binary Counters, 16, 32 bits long
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4005v.zip 101KB Register-Based FIFO for XC3000
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4006v.zip 84KB RAM-Based FIFO for XC4000
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4007v.zip 29KB Boundary Scan Emulator for XC3000
Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4009v.zip 40KB Frequency Synthesizer, FSK Modulator
V.1.10, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xap4021v.zip 114KB 150 MHz Dual-Prescaler Presettable Counters
for XC3000.
V.1.00, Implemented in Viewdraw-LCA
Pre-Unified Libraries
xapp001o.zip 100KB 60 MHz Counters, 8 to 24 bits long
V.2.0.1, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp002o.zip 187KB Loadable Up/Down Counters, 8 to 24 bits long
V.2.0.1, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp002v.zip 197KB Loadable Up/Down Counters, 8 to 24 bits long
V.2.0.1, Implemented in Viewdraw-LCA
Unified Libraries
xapp003o.zip 311KB Synchronous Presettable Up and Down Counters,
8, 12, and 16 bits long
V.2.0.1, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp003v.zip 375KB Synchronous Presettable Up and Down Counters,
8, 12, and 16 bits long
V.2.0.1, Implemented in Viewdraw-LCA
Unified Libraries
xapp004o.zip 225KB Loadable Binary Counters, 16, 32 bits long
V.2.0.1, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp004v.zip 282KB Loadable Binary Counters, 16, 32 bits long
V.2.0.1, Implemented in Viewdraw-LCA
Unified Libraries
xapp005o.zip 68KB Register-Based FIFO for XC3000
V.2.0.1, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp005v.zip 87KB Register-Based FIFO for XC3000
V.2.0.1, Implemented in Viewdraw-LCA
Unified Libraries
xapp006v.zip 84KB RAM-Based FIFO for XC4000
V.1.10, Implemented in Viewdraw-LCA
Unified Libraries
xapp007o.zip 26 Kb Boundary Scan Emulator for XC3000 v2.03,
Implemented in OrCAD 386+ V1.10 Unified
Libraries
Uploaded: 09-17-96
xapp007v.zip 33 Kb Boundary Scan Emulator for XC3000 v2.03,
Implemented in Viewdraw-LCA Unified Libraries
Uploaded: 09-17-96
xapp009o.zip 26KB Frequency Synthesizer, FSK Modulator
V.2.0.1, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp009v.zip 31KB Frequency Synthesizer, FSK Modulator
V.2.0.1, Implemented in Viewdraw-LCA
Unified Libraries
xapp014o.zip 70KB Ultra-Fast Synchronous Counters v1.02,
Implemented in OrCAD 386+ V1.10 Unified
Libraries
Uploaded: 09-17-96
xapp014v.zip 61KB Ultra-Fast Synchronous Counters
V.1.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp021o.zip 90KB 150 MHz Dual-Prescaler Presettable Counters
for XC3000. V.2.01, Implemented in OrCAD
386+ V1.10. Unified Libraries
xapp021v.zip 107KB 150 MHz Dual-Prescaler Presettable Counters
for XC3000.
V.2.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp022o.zip 12KB Adders, Subtractors, and Accumulators in
XC3000. V.1.01, Implemented in OrCAD 386+
V1.10. Unified Libraries
xapp022v.zip 17KB Adders, Subtractors, and Accumulators in
XC3000. V.1.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp023o.zip 64KB Accelerating Loadable Counters in XC4000
V.1.01, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp023v.zip 78KB Accelerating Loadable Counters in XC4000
V.1.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp026o.zip 23KB Multiplexers and Barrel Shifters in XC3000.
V.1.01, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp026v.zip 32KB Multiplexers and Barrel Shifters in XC3000.
V.1.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp028o.zip 5KB Frequency/Phase Comparator for Phase-Locked
Loops. V.1.01, Implemented in OrCAD 386+ V1.
Unified Libraries
xapp028v.zip 6KB Frequency/Phase Comparator for Phase-Locked
Loops. V.1.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp029o.zip 6KB Serial Code Conversion Between BCD and Binary
V.1.01, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp029v.zip 8KB Serial Code Conversion Between BCD and Binary
V.1.01, Implemented in Viewdraw-LCA
Unified Libraries
xapp036a.zip 6KB DRAM Controller for XC7200
ABEL and .pld Behavioral design files
for a 4-port memory controller. Fits
in an XC7236.
xapp044o.zip 39KB High-Performance RAM based FIFO
V.1.00, Implemented in Orcad 386+ V1.10
xapp048o.zip 39KB Xilinx Guided Tour for XACT 5.0
V.1.00, Implemented in OrCAD 386+ V1.10
Unified Libraries
xapp048v.zip 37KB Xilinx Guided Tour for XACT 5.0
V.1.00, Implemented in Viewdraw-LCA
Unified Libraries
xapp049a.zip 18KB Pentium/Synchronous DRAM Controller
Behavioral Design Example for EPLDs
ABEL files, V.1.00
xapp050o.zip 417KB Crossbar Switch in XC4000
V.1.00, Implemented in Orcad 386+ V1.10
xapp050v.zip 362KB Crossbar Switch in XC4000
V.1.00, Implemented in Viewdraw-LCA
Unified Libraries
xapp131h.tar.Z
19 Kb Uploaded: 12-10-1998
170 MHz FIFOs Using the Virtex Block SelectRAM+
(XAPP131), implemented in VHDL and Verilog
For All Platforms
SW Release: All
Category: Documentation, App Note
xapp131h.zip
13 Kb Uploaded: 12-10-1998
170 MHz FIFOs Using the Virtex Block SelectRAM+
(XAPP131), implemented in VHDL and Verilog
For All Platforms
SW Release: All
Category: Documentation, App Note
xapp132.zip
6 Kb Uploaded: 09-27-1999
XAPP132 Virtex Delay Locked Loop Usage VHDL and
Verilog CLKDLL examples.
For All Platforms
Category: Documentation, App Note
xapp134_verilog.tar.Z
644 Kb Uploaded: 12-15-1999
Verilog code for XAPP134, SDRAM design for UNIX
users. First time out in a .tar.Z file format
For All Unix
xapp134_verilog.zip
397 Kb Uploaded: 12-15-1999
Verilog code for XAPP134, SDRAM design which
replaces the old SDRAM_Design.zip files. This is
for PC.
For All Windows
xapp134_vhdl.tar.Z
285 Kb Uploaded: 12-15-1999
VHDL code for XAPP134, SDRAM design for UNIX
users. First time out in a .tar.Z file format
For All Unix
xapp134_vhdl.zip
185 Kb Uploaded: 12-15-1999
VHDL code for XAPP134, SDRAM design which
replaces the old SDRAM_Design_vhdl.zip files.
This is for PC.
For All Windows
xapp136.tar.gz
5 Kb Uploaded: 08-10-1999
XAPP136 reference design update. This is an
updated file per Shekhar Bapat. I will also add
the PC version.
For All Unix
xapp136.zip
7 Kb Uploaded: 08-10-1999
XAPP136 reference design update. This is an
updated file per Shekhar Bapat.
For All Unix
xapp136_vhdl.tar.gz
6 Kb Uploaded: 08-31-1999
XAPP136 VHDL Design files for pipelined and
flowthrough ZBTSRAM controller.
For All Platforms
Category: Documentation, App Note
Dependencies: NONE
xapp136_vhdl.zip
9 Kb Uploaded: 08-31-1999
XAPP136 VHDL Design files for pipelined and
flowthrough ZBTSRAM controller.
For All Platforms
Category: Documentation, App Note
Dependencies: NONE
xapp137.zip
176 Kb Uploaded: 01-03-2000
This archive contains the following PromMAP
design source files for xapp137. These files are
meant to be used seperately from each other and
require no other dependency files. prom_map.v --
Verilog file. prom_map.vhd -- VHDL file.
Prommap.zip -- Foundation Schematic Project
Archive
For All Windows
Dependencies: none
xapp153.zip
8 Kb Uploaded: 06-04-1999
16-bit Status and Control Semaphore register
using Virtex Partial Reconfiguration (XAPP153),
implemented in PERL, Verilog and VHDL.
For All Platforms
SW Release: A1.5i/F1.5i
Category: Documentation, App Note
xapp164.tar.Z
69 Kb Uploaded: 08-11-1999
Tcl scripts for Using Xilinx and Synplify for
Incremental Designing (ECO)
For All Platforms
SW Release: A2.1i
Category: Documentation, App Note
xapp164.zip
46 Kb Uploaded: 08-11-1999
Tcl scripts for Using Xilinx and Synplify for
Incremental Designing (ECO)
For All Platforms
SW Release: A2.1i
Category: Documentation, App Note
xapp165.tar.Z
9 Kb Uploaded: 08-27-1999
Tcl scripts for using Xilinx and Exemplar for
Incremental Design (ECO)
For All Unix
SW Release: A2.1i
Category: Documentation, App Note
xapp165.zip
6 Kb Uploaded: 08-27-1999
Tcl scripts for using Xilinx and Exemplar for
Incremental Design (ECO)
For All Windows
SW Release: A2.1i
Category: Documentation, App Note
xapp174.tar.Z
6 Kb Uploaded: 12-13-1999
XAPP174 Using Delay Locked Loops in Spartan-II
FPGAs, VHDL and Verilog CLKDLL examples.
For All Unix
SW Release: A2.1i/F2.1i
Category: Documentation, App Note
xapp174.zip
7 Kb Uploaded: 12-13-1999
XAPP174 Using Delay Locked Loops in Spartan-II
FPGAs, VHDL and Verilog CLKDLL examples.
For All Windows
SW Release: A2.1i/F2.1i
Category: Documentation, App Note
xapp175.tar.Z
19 Kb Uploaded: 12-13-1999
High Speed FIFOs In Spartan-II FPGAs (XAPP175),
implemented in VHDL and Verilog
For All Unix
SW Release: A2.1i/F2.1i
Category: Documentation, App Note
xapp175.zip
13 Kb Uploaded: 12-13-1999
High Speed FIFOs In Spartan-II FPGAs (XAPP175),
implemented in VHDL and Verilog
For All Platforms
SW Release: A2.1i/F2.1i
Category: Documentation, App Note
xapp200.tar.gz
1348 Kb Uploaded: 01-25-2000
This file contains both the VHDL & Verilog code
for XAPP200. These are the latest versions.
For All Unix
xapp200.zip
1361 Kb Uploaded: 01-25-2000
This file contains both the VHDL & Verilog code
for the 64 bit version of the XAPP200 Reference
design. These are the latest versions.
For All Platforms
xapp200_16.tar.gz
714 Kb Uploaded: 01-25-2000
This file contains both the VHDL & Verilog code
for the 16 bit version of the XAPP200 Reference
design. These are the latest versions.
For All Unix
xapp200_16.zip
729 Kb Uploaded: 01-25-2000
This file contains both the VHDL & Verilog code
for the 16 bit version of the XAPP200 Reference
design. These are the latest versions.
For All Platforms
xapp202.tar.Z
31 Kb Uploaded: 08-27-1999
This file is the reference design for XAPP202
"CAM designs in ATM applications"
For All Unix
xapp202.zip
18 Kb Uploaded: 08-27-1999
This file is the reference design for XAPP202
"CAM designs in ATM applications"
For All Windows
xapp203.tar.Z
62 Kb Uploaded: 12-11-1999
This is the UNIX version of both the VHDL &
Verilog Reference Designs for XAPP203
For All Unix
xapp203.zip
60 Kb Uploaded: 12-11-1999
This is the PC version of both the VHDL &
Verilog Reference Designs for XAPP203
For All Windows
xapp204.tar.Z
58 Kb Uploaded: 12-11-1999
This is the Unix version of both the VHDL &
Verilog Reference Designs for XAPP204
For All Unix
xapp204.zip
54 Kb Uploaded: 12-11-1999
This is the PC version of both the VHDL &
Verilog Reference Designs for XAPP204
For All Windows
xapp205.zip
14 Kb Uploaded: 09-27-1999
Verilog reference design file for XAPP205 "data-
width" conversion FIFOs using Virtex Block
SelectRAM"
For All Windows
xapp208.tar.gz
7 Kb Uploaded: 08-31-1999
The reference design for XAPP208 is in this
file. XAPP208 is the IDCT implementation in
Virtex Devices for MPEG Video Applications.
For All Unix
xapp208.zip
9 Kb Uploaded: 08-31-1999
The reference design for XAPP208 is in this
file. XAPP208 is the IDCT implementation in
Virtex Devices for MPEG Video Applications.
For All Windows
xapp211.tar.gz
64 Kb Uploaded: 02-04-2000
This is the Unix version of both VHDL and
Verilog code for the reference design for
XAPP211.
For All Unix
xapp211.zip
69 Kb Uploaded: 02-04-2000
Reference design file for XAPP211 "PN Generators
using the Virtex SRL Macro"
For All Windows
xapp233.zip
289 Kb Uploaded: 12-10-1999
This is the 622 Mb/s XAPP233 reference design
and implementation files
For All Windows
xapp315.zip
503 Kb Uploaded: 01-04-2000
ZIP file containing documentation, VHDL source
files and testbenches, and CoolRunner CPLD
compiler and fitter files for the I2C Controller
design described in XAPP315
For All Platforms
